software reset stm32 Опции

[123kill12]

Странно у меня работает программная перезагрузка. IWDT работает как надо. и даже когда делал WWDT тоже. но вот программная перезагрузка работает коряво.

сработает при первом запуске, перезагрузит и все. больше не срабатывает. может нужно какой то флаг сбросить. флаги в RCC->CSR (control status reg) я сбрасываю.

сброс генерирую так.
SCB->AIRCR|=0x05FA<<16 | SCB_AIRCR_SYSRESETREQ;

может нужно что то еще????

[123kill12]

#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */

#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */

#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */


static __INLINE void __DSB() { __ASM volatile ("dsb"); }
так эта функция выполняет ассемблерную команду dsb. идем на сайт и читаем

DSB
Data Synchronization Barrier acts as a special kind of memory barrier. No instruction in program order after this instruction executes until this instruction completes. This instruction completes when:
All explicit memory accesses before this instruction complete.
All Cache, Branch predictor and TLB maintenance operations before this instruction complete.
Allowed values are:
SY - Full system DSB operation. This is the default, and can be omitted.
UN - DSB operation only out to the point of unification.
ST - DSB operation that waits only for stores to complete.
UNST - DSB operation that waits only for stores to complete and only out to the point of unification.



Bits 31:16 VECTKEYSTAT[15:0]/ VECTKEY[15:0] Register key
Reads as 0xFA05
On writes, write 0x5FA to VECTKEY, otherwise the write is ignored.
Bit 15 ENDIANESS Data endianness bit
Reads as 0.
0: Little-endian
Bits 14:11 Reserved, must be kept cleared
Bits 10:8 PRIGROUP[2:0]: Interrupt priority grouping field
This field determines the split of group priority from subpriority, see Binary point on page 134.
Bits 7:3 Reserved, must be kept cleared
Bit 2 SYSRESETREQ System reset request
This is intended to force a large system reset of all major components except for debug.
This bit reads as 0.
0: No system reset request
1: Asserts a signal to the outer system that requests a reset.
Bit 1 VECTCLRACTIVE
Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to
this bit, otherwise behavior is unpredictable.
Bit 0 VECTRESET
Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to
this bit, otherwise behavior is unpredictable

SCB->AIRCR = ((0x5FA << 16)|(SCB->AIRCR&(0x07 << 8))|(1 << 2));
и приходим к выводу что я правильно делал.
SCB->AIRCR|=0x05FA<<16 | SCB_AIRCR_SYSRESETREQ;
но я не использовал Data Synchronization Barrier и не ставил в вечный цикл. Попробую