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> how to effectively simulate the large are of via?, in mmic, multilayer
sensen
сообщение Aug 31 2011, 11:57
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i am dealing with a simulation of a power divider in a multilayer mmic technology. the real realization of the device use a large are of metal embedded in a thin substrate layer. i model that by the via. so the model in the EDA has large area of via. So the simulation time is too long to wait.

I have tried the several 2.5D simulator. IE3D, Sonnet, and AWR. only the AXIEM in awr working some faster. about 1 hour to finished the simulation on a dual core 2.5G cpu.

Now i turn to try the 3D simulator. I want to ask the experienced person. what simulator and method is best to use for effectively simulate the large area of via model. i mean short simulation time without loss the accuracy.

thanks in advance.
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