Ассинхронная логика, Можно ли использовать CPLD без клока? Опции

[cornflyer]

да. я уже так делал. просто реализуешь логическую функцию на асинхронных триггерах
вот типичный код проекта для XC9572XL (посредник между DSP и платой сбора данных):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity linux is
port(
LD_DAC : in STD_LOGIC; -- load strobe for DAC
CS_DAC : in STD_LOGIC; -- chip select for LLD and ChW DAC's (Channel width DAC)
RDHB : in STD_LOGIC; -- RDHB' enable signal ('0' - active low level )
RDLB : in STD_LOGIC; -- RDLB' enable signal
REQ : out STD_LOGIC; -- data ready-signal for DSP
DAO : out STD_LOGIC_VECTOR(7 downto 0); -- data for DSP
DTIME : out STD_LOGIC; -- inquiry about dead time
SLD0 : out STD_LOGIC; -- strobe for LLD (low level discriminator)
SLD2 : out STD_LOGIC; -- strobe for ChW (Channel width DAC)
IRQ : in STD_LOGIC; -- data ready-signal from mezzanine:'
IACK : out STD_LOGIC; -- acknowledge from mediator-FPGA clears IRQ:'1'
DIO : in STD_LOGIC_VECTOR(13 downto 0);-- data from mezzanine
IORD : inout STD_LOGIC; -- '0' to output data from Mux to Count(out_port)
DT : in STD_LOGIC;
ConvEn: out STD_LOGIC;
EnaRST : out STD_LOGIC -- OUTPUT DRIVER STARTING VALUE is '1'
);
end linux;
architecture Behavioral of linux is
signal mux:STD_LOGIC_VECTOR(7 downto 0);
signal input:STD_LOGIC:='1';
begin
process(RDHB,DT)
begin
if DT='1' then
IACK<='0';
elsif RDHB'event and RDHB='1' then
IACK<='1';
end if;
end process;
ConvEn<='1';
------------------------------------------------
SLD0<=LD_DAC when CS_DAC='1' else '1';
SLD2<=LD_DAC when CS_DAC='0' else '1';
------------------------------------------------
process(LD_DAC,input)
begin
if (LD_DAC'event and LD_DAC='0') then
EnaRST <= input;
end if;
end process;
------------------------------------------------
DTIME<=DT;
------------------------------------------------
IORD<=(RDLB and RDHB);
REQ<=IRQ;
DAO<=mux when IORD='0' else "ZZZZZZZZ";
mux(0)<=(('0' and (not RDLB)) or (DIO(6) and RDLB));
mux(1)<=(('0' and (not RDLB)) or (DIO(7) and RDLB));
mux(2)<=((DIO(0) and (not RDLB)) or (DIO(8) and RDLB));
mux(3)<=((DIO(1) and (not RDLB)) or (DIO(9) and RDLB));
mux(4)<=((DIO(2) and (not RDLB)) or (DIO(10) and RDLB));
mux(5)<=((DIO(3) and (not RDLB)) or (DIO(11) and RDLB));
mux(6)<=((DIO(4) and (not RDLB)) or (DIO(12) and RDLB));
mux(7)<=((DIO(5) and (not RDLB)) or (DIO(13) and RDLB));
------------------------------------------------
end Behavioral;

да. я уже так делал. просто реализуешь логическую функцию на асинхронных триггерах
вот типичный код проекта для XC9572XL (посредник между DSP и платой сбора данных):
Тут все порты - это внешние ноги PLD

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity linux is
port(
LD_DAC : in STD_LOGIC; -- load strobe for DAC
CS_DAC : in STD_LOGIC; -- chip select for LLD and ChW DAC's (Channel width DAC)
RDHB : in STD_LOGIC; -- RDHB' enable signal ('0' - active low level )
RDLB : in STD_LOGIC; -- RDLB' enable signal
REQ : out STD_LOGIC; -- data ready-signal for DSP
DAO : out STD_LOGIC_VECTOR(7 downto 0); -- data for DSP
DTIME : out STD_LOGIC; -- inquiry about dead time
SLD0 : out STD_LOGIC; -- strobe for LLD (low level discriminator)
SLD2 : out STD_LOGIC; -- strobe for ChW (Channel width DAC)
IRQ : in STD_LOGIC; -- data ready-signal from mezzanine:'
IACK : out STD_LOGIC; -- acknowledge from mediator-FPGA clears IRQ:'1'
DIO : in STD_LOGIC_VECTOR(13 downto 0);-- data from mezzanine
IORD : inout STD_LOGIC; -- '0' to output data from Mux to Count(out_port)
DT : in STD_LOGIC;
ConvEn: out STD_LOGIC;
EnaRST : out STD_LOGIC -- OUTPUT DRIVER STARTING VALUE is '1'
);
end linux;
architecture Behavioral of linux is
signal mux:STD_LOGIC_VECTOR(7 downto 0);
signal input:STD_LOGIC:='1';
begin
process(RDHB,DT)
begin
if DT='1' then
IACK<='0';
elsif RDHB'event and RDHB='1' then
IACK<='1';
end if;
end process;
ConvEn<='1';
------------------------------------------------
SLD0<=LD_DAC when CS_DAC='1' else '1';
SLD2<=LD_DAC when CS_DAC='0' else '1';
------------------------------------------------
process(LD_DAC,input)
begin
if (LD_DAC'event and LD_DAC='0') then
EnaRST <= input;
end if;
end process;
------------------------------------------------
DTIME<=DT;
------------------------------------------------
IORD<=(RDLB and RDHB);
REQ<=IRQ;
DAO<=mux when IORD='0' else "ZZZZZZZZ";
mux(0)<=(('0' and (not RDLB)) or (DIO(6) and RDLB));
mux(1)<=(('0' and (not RDLB)) or (DIO(7) and RDLB));
mux(2)<=((DIO(0) and (not RDLB)) or (DIO(8) and RDLB));
mux(3)<=((DIO(1) and (not RDLB)) or (DIO(9) and RDLB));
mux(4)<=((DIO(2) and (not RDLB)) or (DIO(10) and RDLB));
mux(5)<=((DIO(3) and (not RDLB)) or (DIO(11) and RDLB));
mux(6)<=((DIO(4) and (not RDLB)) or (DIO(12) and RDLB));
mux(7)<=((DIO(5) and (not RDLB)) or (DIO(13) and RDLB));
------------------------------------------------
end Behavioral;

[Harbour]

есть даже ресурс в сети посвященный переводу синхронных схем в асинхронные - бонусы состоят в пониженном потреблении и отсутствии ярко выраженных электромагнитных излучений при защелкивании кипы триггеров по одному фронту.