У Imsys есть
статья, обсуждающая архитектуру процессоров. Там можно найти много интересного. Например:
CEO of MIPS Technologies now admits that the RISC revolution has been a mistake. He says it built on a balance between CPU and memory speeds, but unfortunately that balance was transient.
The main problem with RISC is that its clock frequency is assumed to be the maximum frequency the arithmetic/logic unit (ALU) can handle, and that memory accesses need to match this frequency.
The increasing “speed gap” must be bridged by increasing the size of the cache. The cache consumes more silicon area and power than the processor core itself. Thus, this is a RISC disadvantage that grows with time.
Нужен совет мастеров., совет для новичка, то есть для меня :-)
Apr 25 2008, 17:12
