ГЫ
Да входов выходов небыло - думал автоматически добавляет (галочка то стоит). Вот: (скажите - какая максимальная частота на которой он может работать ?)
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* Final Report *
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Final Results
RTL Top Level Output File Name : jjj.ngr
Top Level Output File Name : jjj
Output Format : NGC
Optimization Goal : speed
Keep Hierarchy : no
Design Statistics
# IOs : 19
Cell Usage :
# BELS : 1
# GND : 1
# IO Buffers : 19
# IBUF : 3
# OBUF : 16
# Others : 1
# SR16CE : 1
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Device utilization summary:
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Selected Device : 2s15cs144-6
Number of bonded IOBs: 19 out of 90 21%
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TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
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No clock signals found in this design
Timing Summary:
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Speed Grade: -6
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 5.703ns
Timing Detail:
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All values displayed in nanoseconds (ns)
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Timing constraint: Default path analysis
Delay: 5.703ns (Levels of Logic = 1)
Source: U1:Q<15> (PAD)
Destination: BusOutput0<15> (PAD)
Data Path: U1:Q<15> to BusOutput0<15>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
SR16CE:Q<15> 1 0.000 1.035 U1 (BusOutput0_15_OBUF)
OBUF:I->O 4.668 BusOutput0_15_OBUF (BusOutput0<15>)
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Total 5.703ns (4.668ns logic, 1.035ns route)
(81.9% logic, 18.1% route)
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Вопрос по XST через Алдек
Aug 9 2005, 06:27
