Digilent программатор Xilinx, кто пользовал? Опции

[ADA007]

Приветствую всех форумчан!

Подскажите, кто пользовал данный девайс ? Действительно ли "Compatible with all Xilinx tools" ? И все ли там так гладко, как они пишут? Привлекает цена самой ftdi-ки, но смущают подводные камни.

ЗЫ. не зря же здесь лепили полную копию оригинального DLC10...

[toshas]

Кто-нибудь знает в чем отличие "новых" SMT2 и HS3 ?
Все сводится к одному доп. пину сброса ?
Какая ножка FT2232 им управляет ?

http://store.digilentinc.com/all-products/jtag-programmers/

"The Xilinx Tools occasionally require the processor core of the Zynq-7000 to be reset during debug operations. The
Zynq platform processor has a pin dedicated for this purpose (PS_SRST_B). Driving the PS_SRST_B pin low causes
the processor to reset while maintaining any existing break points and watch points. The JTAG-HS3 is capable of
driving this pin low under the instruction of Xilinx’s SDK during debugging operations. In order for this to work, pin
14 of Xilinx JTAG header on the target board must be connected to the PS_SRST_B pin of the Zynq (see Figs. 3 & 4).

The JTAG-HS3 uses an open drain buffer to drive pin 14 of the Xilinx JTAG header (see Fig. 5). This allows the HS3 to
drive the PS_SRST_B pin when VCC_MIO1 is referenced to a different voltage than VCCO_0 (see Fig. 6).

Should an accidental short occur between pin 14 and GND, the 100 ohm series resistor protects the buffer from
being damaged. While this resistor protects the buffer from being damaged, it also limits the drive strength of the
buffer. Therefore, it is necessary for the pull-up resistor (RPU) used to establish the voltage level on PS_SRST_B to
be greater than or equal to 1.5K ohms. At the time of writing, Xilinx ZC702, Xilinx ZC706, and Avnet® MicroZed™ all
feature 10K pull-ups on pin 14 of the their respective Xilinx JTAG headers. For compatibility with other evaluation
platforms, please consult the manufacturer’s schematic."


Спасибо!

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