Цитата(CaPpuCcino @ Oct 17 2008, 12:37)
люди добрые, объясните, какой бит какому будет присвоен в Верилоге в следующем случае:
module little_big_assignment;
reg [0:7] little;
reg [3:0] big;
initial
little=big;
endmodule
ИМХО :
little[0:3] = 3'bxxxx
little[4] = big[3]
little[5] = big[2]
little[6] = big[1]
little[7] = big[0]
ответ основываю на стандарте :
3.3.1 Specifying vectors
Цитата
The range specification gives addresses to the individual bits in a multibit net or reg. The most significant bit
specified by the msb constant expression is the left-hand value in the range and the least significant bit spec-
ified by the lsb constant expression is the righthand value in the range.
Как я понял msb всегда стоит слева, lsb справа. не важно какие индексы. И арифметика всегда работает по этим правилам.
Косвенное подтверждение этому
4.2.1 Vector bit-select and part-select addressing
Цитата
Example 1 The following example specifies the single bit of acc vector that is addressed by the operand
index.
acc[index]
The actual bit that is accessed by an address is, in part, determined by the declaration of acc. For instance,
each of the declarations of acc shown in the next example causes a particular value of index to access a
different bit:
reg [15:0] acc;
reg [2:17] acc