Первый проект на плис и Lattice в часности. Полностью с нуля пытаюсь сосздать проект и залить в чип.
На схему закинул один элемент 2И, входы соединил, in out, назначил пины, нажимаю Run, имею лог.
Насколько я понял должен появится .jed файл, но его нет, в чем проблема может быть?
CODE
Starting: "pgr_project save "D:/Projects/Soft/soft_Lattice_0/impl1/impl1.xcf""
Starting: "pgr_project close"
sch2vlog -FPGA -i D:/Projects/Soft/soft_Lattice_0/main.sch -o D:/Projects/Soft/soft_Lattice_0/impl1/main.v -gui -msgset D:/Projects/Soft/soft_Lattice_0/promote.xml
Done: completed successfully
************************************************************
** Lattice Synthesis Engine **
************************************************************
synthesis -f "Lattice_0_impl1_lattice.synproj"
synthesis: version Diamond (64-bit) 3.10.2.115
Copyright © 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright © 1995 AT&T Corp. All rights reserved.
Copyright © 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright © 2001 Agere Systems All rights reserved.
Copyright © 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Sat Sep 22 00:11:58 2018
Command Line: synthesis -f Lattice_0_impl1_lattice.synproj -gui
INFO - Lattice Synthesis Engine Launched.
Synthesis options:
The -a option is MachXO2.
The -s option is 2.
The -t option is CSBGA132.
The -d option is LCMXO2-1200ZE.
Using package CSBGA132.
Using performance grade 2.
##########################################################
### Lattice Family : MachXO2
### Device : LCMXO2-1200ZE
### Package : CSBGA132
### Speed : 2
##########################################################
INFO - User-Selected Strategy Settings
Optimization goal = Balanced
Top-level module name = main.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1
Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO
Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p D:/Projects/Soft/soft_Lattice_0 (searchpath added)
-p C:/Lattice/lscc/diamond/3.10_x64/ispfpga/xo2c00/data (searchpath added)
-p D:/Projects/Soft/soft_Lattice_0/impl1 (searchpath added)
-p D:/Projects/Soft/soft_Lattice_0 (searchpath added)
Verilog design file = D:/Projects/Soft/soft_Lattice_0/impl1/main.v
NGD file = Lattice_0_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...
Analyzing Verilog file C:/Lattice/lscc/diamond/3.10_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file d:/projects/soft/soft_lattice_0/impl1/main.v. VERI-1482
Analyzing Verilog file C:/Lattice/lscc/diamond/3.10_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): main
INFO - d:/projects/soft/soft_lattice_0/impl1/main.v(3): compiling module main. VERI-1018
INFO - C:/Lattice/lscc/diamond/3.10_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(43): compiling module AND2. VERI-1018
Last elaborated design is main()
Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c1200.nph' in environment: C:/Lattice/lscc/diamond/3.10_x64/ispfpga.
Package Status: Final Version 1.42.
Top-level module name = main.
WARNING - d:/projects/soft/soft_lattice_0/impl1/main.v(9): Removing unused instance . VDB-5034
GSR will not be inferred because no asynchronous signal was found in the netlist.
Applying 200.000000 MHz constraint to all clocks
WARNING - No user .sdc file.
Results of NGD DRC are available in main_drc.log.
Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/or5g00/data/orc5glib.ngl'...
Running DRC...
WARNING - logical net 'GND_net' has no load.
WARNING - DRC complete with 1 warnings.
Design Results:
7 blocks expanded
completed the first expansion
All blocks are expanded and NGD expansion is successful.
Writing NGD file Lattice_0_impl1.ngd.
################### Begin Area Report (main)######################
Number of register bits => 0 of 1595 (0 % )
AND2 => 1
GSR => 1
IB => 1
OB => 1
################### End Area Report ##################
################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################
################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 0
Clock Enable Nets
Number of Clock Enables: 0
Top 0 highest fanout Clock Enables:
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
Net : f2_c, loads : 2
Net : o_c, loads : 1
Net : o, loads : 0
################### End Clock Report ##################
Peak Memory Usage: 49.711 MB
--------------------------------------------------------------
Elapsed CPU time for LSE flow : 0.265 secs
--------------------------------------------------------------
Done: completed successfully
************************************************************
** Map Design **
************************************************************
map -a "MachXO2" -p LCMXO2-1200ZE -t CSBGA132 -s 2 -oc Commercial "Lattice_0_impl1.ngd" -o "Lattice_0_impl1_map.ncd" -pr "Lattice_0_impl1.prf"
-mp "Lattice_0_impl1.mrp" -lpf "D:/Projects/Soft/soft_Lattice_0/impl1/Lattice_0_impl1.lpf" -lpf "D:/Projects/Soft/soft_Lattice_0/Lattice_0.lpf" -c 0
map: version Diamond (64-bit) 3.10.2.115
Copyright © 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright © 1995 AT&T Corp. All rights reserved.
Copyright © 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright © 2001 Agere Systems All rights reserved.
Copyright © 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Process the file: Lattice_0_impl1.ngd
Picdevice="LCMXO2-1200ZE"
Pictype="CSBGA132"
Picspeed=2
Remove unused logic
Do not produce over sized NCDs.
Part used: LCMXO2-1200ZECSBGA132, Performance used: 2.
Loading device for application map from file 'xo2c1200.nph' in environment: C:/Lattice/lscc/diamond/3.10_x64/ispfpga.
Package Status: Final Version 1.42.
Running general design DRC...
Removing unused logic...
Optimizing...
Design Summary:
Number of registers: 0 out of 1595 (0%)
PFU registers: 0 out of 1280 (0%)
PIO registers: 0 out of 315 (0%)
Number of SLICEs: 0 out of 640 (0%)
SLICEs as Logic/ROM: 0 out of 640 (0%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 0 out of 640 (0%)
Number of LUT4s: 0 out of 1280 (0%)
Number used as logic LUTs: 0
Number used as distributed RAM: 0
Number used as ripple logic: 0
Number used as shift registers: 0
Number of PIO sites used: 2 + 4(JTAG) out of 105 (6%)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
Number of clocks: 0
Number of Clock Enables: 0
Number of LSRs: 0
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net f2_c: 1 loads
Number of warnings: 0
Number of errors: 0
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 36 MB
Dumping design to file Lattice_0_impl1_map.ncd.
ncd2vdb "Lattice_0_impl1_map.ncd" ".vdbs/Lattice_0_impl1_map.vdb"
Loading device for application ncd2vdb from file 'xo2c1200.nph' in environment: C:/Lattice/lscc/diamond/3.10_x64/ispfpga.
Done: completed successfully
************************************************************
** Place & Route Design **
************************************************************
mpartrce -p "Lattice_0_impl1.p2t" -f "Lattice_0_impl1.p3t" -tf "Lattice_0_impl1.pt" "Lattice_0_impl1_map.ncd" "Lattice_0_impl1.ncd"
---- MParTrce Tool ----
Removing old design directory at request of -rem command line option to this program.
par -f Lattice_0_impl1.p2t.tmp0 Lattice_0_impl1_map.ncd Lattice_0_impl1.dir\5_1.dir Lattice_0_impl1.prf -gui
Output design is: Lattice_0_impl1
Output DIR is: .
Preference file is: Lattice_0_impl1.prf
Exiting mpartrce with exit code 0
Done: completed successfully
Делай что должен и будь что будет.
Lattice Diamond первый проект.
Sep 22 2018, 04:49
