Warning'и в Xilinx "At least one timing constraint is impossible to meet" Опции

[евгенийкочин]

Работая над проектом в ISE встретился такой ворнинг
At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1."
Покопавшись в комьюнити Xilinx'а я не нашел ничего лучше, как взять и сделать также как мне и посоветовал компилятор т.е. установил в консоли переменную XIL_TIMING_ALLOW_IMPOSSIBLE в 1. Появился следующий ворнинг
WARNING Xst:3201 - TIMESPEC 'TS_CLK_FPGA_N' is related to another TIMESPEC which is not defined.
WARNING Xst:3201 - TIMESPEC 'TS_FR_N' is related to another TIMESPEC which is not defined.
Внимание вопрос: чем опасны эти ворнинги и нужно было ли исправлять первый?