IAR + Jlink + отладка в SDRAM Опции

[Alex_rav(зеленин...]

Доброго времени суток.

Неделю терзаю отладочную плату LPC4357-EVB. Хочу научится исполнятся и отлаживаться из SDRAM MT48LC16M16A2, которая есть на плате. Никто не может поделится *.mac файлом для отладки из SDRAM для Jlink для семейства LPC43xx?


Вот мой код, который не работает

CODE

__var EMCClock;





__var FUNC0;
__var FUNC1;
__var FUNC2;
__var FUNC3;
__var FUNC4;
__var FUNC5;
__var FUNC6;
__var FUNC7;



__var MD_PUP;
__var MD_BUK;
__var MD_PLN;
__var MD_PDN;
__var MD_EHS;
__var MD_EZI;
__var MD_ZI;
__var MD_EHD0;
__var MD_EHD1;
__var MD_EHD2;
__var MD_PLN_FAST;




EMC_SDRAM_REFRESH(ns)
{
EMCClock = 108000000;
__var tCLK_ns;
tCLK_ns = ((double)EMCClock / 16000000000 ); // CCLK period in ns
return (int)((double)(ns) * tCLK_ns + 1); // convert ns to CCLKs
}

NS_2_CLKS(ns)
{
EMCClock = 108000000;
__var tCLK_ns;
tCLK_ns = ((double)EMCClock / 1000000000.0 ); // CCLK period in ns
return (int)((double)(ns) * tCLK_ns ); // convert ns to CCLKs
}


__setupEMC(){
__var tmpclk;
__var tempReg;
__var freq;
__var psel;
__var pval;

EMCClock = 108000000;

FUNC0 = 0x0;
FUNC1 = 0x1;
FUNC2 = 0x2;
FUNC3 = 0x3;
FUNC4 = 0x4;
FUNC5 = 0x5;
FUNC6 = 0x6;
FUNC7 = 0x7;

MD_PUP = (0x0 << 3);
MD_BUK = (0x1 << 3);
MD_PLN = (0x2 << 3);
MD_PDN = (0x3 << 3);
MD_EHS = (0x1 << 5);
MD_EZI = (0x1 << 6);
MD_ZI = (0x1 << 7);
MD_EHD0 = (0x1 << 8);
MD_EHD1 = (0x1 << 9);
MD_EHD2 = (0x3 << 8);
MD_PLN_FAST = (MD_PLN | MD_EZI | MD_ZI | MD_EHS);

//Setup CGU


//CGU_SetXTALOSC(12000000);
__writeMemory32(__readMemory32(0x40050018, "Memory") & ~(1<<2) , 0x40050018, "Memory"); // LPC_CGU->XTAL_OSC_CTRL &= ~(1<<2);

//CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
__writeMemory32(__readMemory32(0x40050018, "Memory") & ~(1<<0) , 0x40050018, "Memory"); // LPC_CGU->XTAL_OSC_CTRL &= ~CGU_CTRL_EN_MASK;

__delay(100); ///*Delay for stable clock


//CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
tempReg = __readMemory32(0x40050044, "Memory"); //CGU_ADDRESS32(LPC_CGU->PLL1_CTRL);
tempReg &= ~(0xF<<24);
tempReg |= (6<<24) | (1<<11);
__writeMemory32(tempReg , 0x40050044, "Memory"); //CGU_ADDRESS32(LPC_CGU->PLL1_CTRL) = tempReg;


//CGU_SetPLL1(9);
freq = 12000000 * 9;

tempReg = __readMemory32(0x40050044, "Memory"); //CGU_ADDRESS32(LPC_CGU->PLL1_CTRL);
tempReg &= ~((1<<6) | (1<<1) | (1<<7) | (0x03<<8) | (0xFF<<16) | (0x03<<12));// LPC_CGU->PLL1_CTRL &= ~(CGU_PLL1_FBSEL_MASK | //0x06000800 CGU_PLL1_BYPASS_MASK | CGU_PLL1_DIRECT_MASK | (0x03<<8) | (0xFF<<16) | (0x03<<12));
__writeMemory32(tempReg , 0x40050044, "Memory");

pval=1;
while(2*(pval)*freq < 156000000)
{
psel++;
pval*=2;
}
tempReg |= ((9-1)<<16) | (0<<12) | (psel<<8) | (1<<6); //0x06080840
__writeMemory32(tempReg , 0x40050044, "Memory");

//CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
tempReg = __readMemory32(0x40050044, "Memory"); //CGU_ADDRESS32(LPC_CGU->PLL1_CTRL); //PLL1_CTRL &= ~CGU_CTRL_EN_MASK;
tempReg &= ~1;
__writeMemory32(tempReg , 0x40050044, "Memory");

while((__readMemory32(0x40050040, "Memory")&1) == 0x0);

//CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M4);
tempReg = __readMemory32(0x4005006C, "Memory"); //CGU_ADDRESS32(LPC_CGU->CGU_BASE_M4);
tempReg &= ~(0xF<<24);
tempReg |= (9<<24) | (1<<11);
__writeMemory32(tempReg , 0x4005006C, "Memory"); //CGU_ADDRESS32(CGU_BASE_M4) = tempReg;

//PIN

__writeMemory32(0x000000F3, 0x4008609C, "Memory"); // D0
__writeMemory32(0x000000F3, 0x400860A0, "Memory"); // D1
__writeMemory32(0x000000F3, 0x400860A4, "Memory"); // D2
__writeMemory32(0x000000F3, 0x400860A8, "Memory"); // D3
__writeMemory32(0x000000F3, 0x400860AC, "Memory"); // D4
__writeMemory32(0x000000F3, 0x400860B0, "Memory"); // D5
__writeMemory32(0x000000F3, 0x400860B4, "Memory"); // D6
__writeMemory32(0x000000F3, 0x400860B8, "Memory"); // D7

__writeMemory32(0x000000F2, 0x40086290, "Memory"); // D8
__writeMemory32(0x000000F2, 0x40086294, "Memory"); // D9
__writeMemory32(0x000000F2, 0x40086298, "Memory"); // D10
__writeMemory32(0x000000F2, 0x4008629C, "Memory"); // D11
__writeMemory32(0x000000F2, 0x40086280, "Memory"); // D12
__writeMemory32(0x000000F2, 0x40086284, "Memory"); // D13
__writeMemory32(0x000000F2, 0x40086288, "Memory"); // D14
__writeMemory32(0x000000F2, 0x4008628C, "Memory"); // D15

__writeMemory32(0x000000B3, 0x40086124, "Memory"); // A0
__writeMemory32(0x000000B3, 0x40086128, "Memory"); // A1
__writeMemory32(0x000000B3, 0x4008612C, "Memory"); // A2
__writeMemory32(0x000000B3, 0x40086130, "Memory"); // A3
__writeMemory32(0x000000B3, 0x40086134, "Memory"); // A4
__writeMemory32(0x000000B2, 0x40086080, "Memory"); // A5
__writeMemory32(0x000000B2, 0x40086084, "Memory"); // A6
__writeMemory32(0x000000B2, 0x40086088, "Memory"); // A7

__writeMemory32(0x000000B3, 0x40086120, "Memory"); // A8
__writeMemory32(0x000000B3, 0x4008611C, "Memory"); // A9
__writeMemory32(0x000000B2, 0x40086118, "Memory"); // A10
__writeMemory32(0x000000B2, 0x40086108, "Memory"); // A11
__writeMemory32(0x000000B2, 0x40086104, "Memory"); // A12
__writeMemory32(0x000000B2, 0x40086100, "Memory"); // A13
__writeMemory32(0x000000B1, 0x40086320, "Memory"); // A14


__writeMemory32(MD_PLN_FAST+FUNC3, 0x40086324, "Memory"); //DYCS0//scu_pinmux( 6 , 9 , MD_PLN_FAST , 3 );//DYCS0
__writeMemory32(MD_PLN_FAST+FUNC3, 0x40086328, "Memory"); //DQMOUT1//scu_pinmux( 6 , 10 , MD_PLN_FAST , 3 );//DQMOUT1
__writeMemory32(MD_PLN_FAST+FUNC3, 0x4008632C, "Memory"); //CKEOUT0//scu_pinmux( 6 , 11 , MD_PLN_FAST , 3 );//CKEOUT0
__writeMemory32(MD_PLN_FAST+FUNC3, 0x40086330, "Memory"); //DQMOUT0//scu_pinmux( 6 , 12 , MD_PLN_FAST , 3 );//DQMOUT0


__writeMemory32(MD_PLN_FAST+FUNC3, 0x40086098, "Memory"); //scu_pinmux(0x1, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_6: WE (function 0) errata */
__writeMemory32(MD_PLN_FAST+FUNC3, 0x40086310, "Memory"); //scu_pinmux(0x6, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_4: CAS (function 0) > CAS# errata */
__writeMemory32(MD_PLN_FAST+FUNC3, 0x40086314, "Memory"); //scu_pinmux(0x6, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_5: RAS (function 0) > RAS# errata */


__writeMemory32(MD_PLN_FAST+FUNC0, 0x40086C00, "Memory"); //LPC_SCU_CLK(0) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK0: EXTBUS_CLK0 (function 0, from datasheet) > CLK ds */


//Static setup

__writeMemory32(NS_2_CLKS(55), 0x4000524C, "Memory"); // LPC_EMC->STATICWAITRD2 = NS_2_CLKS(55);
__writeMemory32(0x81, 0x40005240, "Memory"); // LPC_EMC->STATICCONFIG2 = /*1<<19| */0x81;
__writeMemory32(NS_2_CLKS(10), 0x40005248, "Memory"); // LPC_EMC->STATICWAITOEN2 = NS_2_CLKS(10);
__writeMemory32(NS_2_CLKS(10), 0x40005244, "Memory"); // LPC_EMC->STATICWAITWEN2 = NS_2_CLKS(10);
__writeMemory32(NS_2_CLKS(55), 0x40005250, "Memory"); // LPC_EMC->STATICWAITPAG2 = NS_2_CLKS(55);
__writeMemory32(NS_2_CLKS(55), 0x40005254, "Memory"); // LPC_EMC->STATICWAITWR2 = NS_2_CLKS(55);
__writeMemory32(NS_2_CLKS(55), 0x40005258, "Memory"); // LPC_EMC->STATICWAITTURN2 = NS_2_CLKS(55); /* Select EMC clock-out */

//Dynamic setup

__writeMemory32(0x00000001, 0x40005000, "Memory"); // LPC_EMC->CONTROL = 0x00000001;
__writeMemory32(0x00000000, 0x40005008, "Memory"); // LPC_EMC->CONFIG = 0x00000000;
__writeMemory32(((0<<14) + (3<<9) + (1<<7)), 0x40005100, "Memory"); // LPC_EMC->DYNAMICCONFIG0 = 0<<14 | 3<<9 | 1<<7; /* 256Mb, 16Mx16, 4 banks, row=13, column=9 */

__writeMemory32(0x00000303, 0x40005104, "Memory"); // LPC_EMC->DYNAMICRASCAS0 = 0x00000303; /* 1 RAS, 3 CAS latency */
__writeMemory32(0x00000001, 0x40005028, "Memory"); // LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */


__writeMemory32(NS_2_CLKS(20), 0x40005030, "Memory"); // LPC_EMC->DYNAMICRP = NS2CLK(pclk, 20);
__writeMemory32(NS_2_CLKS(42), 0x40005034, "Memory"); // LPC_EMC->DYNAMICRAS = NS2CLK(pclk, 42);
__writeMemory32(NS_2_CLKS(63), 0x40005038, "Memory"); // LPC_EMC->DYNAMICSREX = NS2CLK(pclk, 63);
__writeMemory32(0x00000005, 0x4000503C, "Memory"); // LPC_EMC->DYNAMICAPR = 0x00000005;
__writeMemory32(0x00000005, 0x40005040, "Memory"); // LPC_EMC->DYNAMICDAL = 0x00000005;
__writeMemory32(0x00000002, 0x40005044, "Memory"); // LPC_EMC->DYNAMICWR = 2;
__writeMemory32(NS_2_CLKS(63), 0x40005048, "Memory"); // LPC_EMC->DYNAMICRC = NS2CLK(pclk, 63);
__writeMemory32(NS_2_CLKS(63), 0x4000504C, "Memory"); // LPC_EMC->DYNAMICRFC = NS2CLK(pclk, 63);
__writeMemory32(NS_2_CLKS(63), 0x40005050, "Memory"); // LPC_EMC->DYNAMICXSR = NS2CLK(pclk, 63);
__writeMemory32(NS_2_CLKS(14), 0x40005054, "Memory"); // LPC_EMC->DYNAMICRRD = NS2CLK(pclk, 14);
__writeMemory32(0x00000002, 0x40005058, "Memory"); // LPC_EMC->DYNAMICMRD = 0x00000002;

__delay(100);

__writeMemory32(0x00000183, 0x40005020, "Memory"); //LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */

__delay(200);

__writeMemory32(0x00000103, 0x40005020, "Memory"); // LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */

__writeMemory32(EMC_SDRAM_REFRESH(70), 0x40005024, "Memory"); // LPC_EMC->DYNAMICREFRESH = EMC_SDRAM_REFRESH(pclk,70); /* ( n * 16 ) -> 32 clock cycles */

__delay(200);

tmpclk = 15625*EMCClock/1000000000/16;

__writeMemory32(tmpclk, 0x40005024, "Memory"); // LPC_EMC->DYNAMICREFRESH = tmpclk; /* ( n * 16 ) -> 736 clock cycles -> 15.330uS at 48MHz <= 15.625uS ( 64ms / 4096 row ) */EMC_CONTROL
__writeMemory32(0x00000083, 0x40005020, "Memory"); // LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */


tempReg = __readMemory32((0x28000000 | (3<<4| 3)<<11), "Memory"); //temp = *((volatile uint32_t *)(SDRAM_ADDR_BASE | (3<<4| 3)<<11)); /* 4 burst, 3 CAS latency */

__writeMemory32(0x00000000, 0x40005020, "Memory"); //LPC_EMC->DYNAMICCONTROL = 0x00000000; /* Issue NORMAL command */

//[re]enable buffers
__writeMemory32(__readMemory32(0x40005100, "Memory") |(1<<19) , 0x40005100, "Memory"); // LPC_EMC->DYNAMICCONFIG0 |= 1<<19;


__writeMemory32(0x01020304, 0x28000020, "Memory");
if(__readMemory32(0x28000020, "Memory") != 0x01020304)
__message "fail\n";
else
__message "not fail\n";


__writeMemory32(0x28000000, 0x40043100, "Memory"); // map SPIFI to shadow area at address 0
}

__releaseCoreReset()
{
__writeMemory32((~(__readMemory32(0x40053154,"Memory"))) & (~(1<<24)),0x40053104,"Memory");
}

__loadLoopCode()
{
__writeMemory32(0x00001F00,0x28080000,"Memory"); /* dummy stack pointer */
__writeMemory32(0x000000D5,0x2880004,"Memory"); /* reset handler */
__writeMemory32(0xE7FEE7FE,0x280800D4,"Memory"); /* jump to itself instruction for M0a */
__writeMemory32(0x28080000,0x40043404,"Memory"); /* M0 shadow pointer. */
}

execUserReset()
{
__message "execUserReset\n";
__setupEMC();
__releaseCoreReset();
__message "execUserReset Finish\n";
}

execUserPreload(){
__message "execUserPreload\n";
__setupEMC();
__loadLoopCode();
__releaseCoreReset();
__message "execUserPreload Finish\n";
}

IAR выдает:

Tue Apr 16, 2013 09:16:42: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\NXP\LPC43xx_extRAM.mac
Tue Apr 16, 2013 09:16:42: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\NXP\Trace_LPC18xx_LPC43xx.dmac
Tue Apr 16, 2013 09:17:06: Sign on message from :
Segger JLink ARM JTAG
Tue Apr 16, 2013 09:17:06: execUserPreload
Tue Apr 16, 2013 09:17:07: not fail
Tue Apr 16, 2013 09:17:07: execUserPreload Finish
Tue Apr 16, 2013 09:17:07: 7820 bytes downloaded and verified (16.28 Kbytes/sec)
Tue Apr 16, 2013 09:17:07: Warning: Target inconsistency detected in Memory range 0x28000000-0x28000113
Tue Apr 16, 2013 09:17:07: Warning: Target inconsistency detected in Memory range 0x28000140-0x28001EB6
Tue Apr 16, 2013 09:17:08: Warning: There were warnings during download, see Log Window
Tue Apr 16, 2013 09:17:08: Loaded debugee: D:\Documents\ÌÊ\LPC43xx\LPC4300-demos\Examples\LCD_ExtSDRAM\EWARM\LPC4350_IntSRAM\Exe\LCD_ExtSDRAM.out
Tue Apr 16, 2013 09:17:09: WinRDI CPUread APSR failed

[RDI Error: 9] Error message should have been found on target
Tue Apr 16, 2013 09:17:09: Target reset
Tue Apr 16, 2013 09:17:09: Failed to load debugee: D:\Documents\ÌÊ\LPC43xx\LPC4300-demos\Examples\LCD_ExtSDRAM\EWARM\LPC4350_IntSRAM\Exe\LCD_ExtSDRAM.out