STM32 Timer1 Gated Mode: Фича? Или бага?, Странно всё это... Опции

[HHIMERA]

Имеем самопроизвольный запуск TIM1 в режиме Gated Mode при Update generation…
STM32F103... простенький код...

CODE

//===============================================================================

RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // TIM2 clock enable (Master)

TIM2->PSC = 0;
TIM2->ARR = 79;
TIM2->CCR1 = 16;

TIM2->CCMR1 |= (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1FE); // PWM Mode2

TIM2->CR1 |= TIM_CR1_OPM; // Select One-pulse mode

TIM2->CR2 |= TIM_CR2_MMS_2; // MMS=100 Compare - OC1REF signal is used as trigger output (TRGO)

//===============================================================================

RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // TIM1 clock enable (Slave)

TIM1->PSC = 0;
TIM1->ARR = 7;
TIM1->CCR1 = 6;

TIM1->CCMR1 |= (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1); // PWM Mode1

TIM1->SMCR |= (TIM_SMCR_TS_0); // TS=001 Internal Trigger 1 (ITR1)
TIM1->SMCR |= (TIM_SMCR_SMS_0 | TIM_SMCR_SMS_2); // SMS=101 Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high.

TIM1->CR1 |= TIM_CR1_CEN; // Counter Enable

//===============================================================================

__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();

TIM1->EGR |= TIM_EGR_UG;

__NOP(); // TIM1 запускается, что странно
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();

Тот же код, но с TIM8 вместо TIM1...

CODE

//===============================================================================

RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // TIM2 clock enable (Master)

TIM2->PSC = 0;
TIM2->ARR = 79;
TIM2->CCR1 = 16;

TIM2->CCMR1 |= (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1FE); // PWM Mode2

TIM2->CR1 |= TIM_CR1_OPM; // Select One-pulse mode

TIM2->CR2 |= TIM_CR2_MMS_2; // MMS=100 Compare - OC1REF signal is used as trigger output (TRGO)

//===============================================================================

RCC->APB2ENR |= RCC_APB2ENR_TIM8EN; // TIM8 clock enable (Slave)

TIM8->PSC = 0;
TIM8->ARR = 7;
TIM8->CCR1 = 6;

TIM8->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; // PWM Mode1

TIM8->SMCR |= (TIM_SMCR_TS_0); // TS=001 Internal Trigger 1 (ITR1)
TIM8->SMCR |= (TIM_SMCR_SMS_0 | TIM_SMCR_SMS_2); // SMS=101 Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high.

TIM8->CR1 |= TIM_CR1_CEN; // Counter Enable

//===============================================================================

__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();

TIM8->EGR |= TIM_EGR_UG;

__NOP(); // TIM8 не запускается, как и положено
__NOP(); // Другие таймера, вместо TIM8, с учётом коррекции бита TS, тоже не запускаются
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();

Такая лажа с TIM1 Gated Mode в STM32F100, STM32F103, STM32F205, STM32F407 и STM32F051...

Сообщение отредактировал HHIMERA - May 22 2013, 13:14

Причина редактирования: [codebox] для длинного кода, [code] - для короткого!!!