Virtex5 + PCIe 4-lane размещение GTX, Ошибка Опции

[StrangerX]

Доброго времени суток!

Плата самодельная:
4-lane PCIe, 2 модуля FC 2Gb, 2 DDR2, XC5VFX30T.

Прошу помощи.

Пытаюсь подключить в XPS PLB_V46_PCIE.

Получаю ошибку:

Код

ERROR:Place:1042 - Unroutable Placement! An IPAD / GT component pair have been
   found that are not placed at a routable IPAD / GT site pair. The IPAD
   component <plbv46_pcie_0_RXP_pin<1>> is placed at site <IPAD_X1Y9>. The
   corresponding GT component
   <plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i> is placed at site
   <GTX_DUAL_X0Y3>. The IPAD can route to the GT <RXP1> pin only if the load
   component is placed at an offset of (-2, -2) with respect to the driver
   component. This placement is UNROUTABLE in PAR and therefore, this error
   condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
   < PIN "plbv46_pcie_0_RXP_pin_1_IBUF.O" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN
   "plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i.RXP1" CLOCK_DEDICATED_ROUTE =
   FALSE; >
ERROR:Place:1038 - Unroutable Placement! An IPAD / GT component pair have been
   found that are not placed at a routable IPAD / GT site pair. The IPAD
   component <plbv46_pcie_0_RXN_pin<1>> is placed at site <IPAD_X1Y8>. The
   corresponding GT component
   <plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i> is placed at site
   <GTX_DUAL_X0Y3>. The IPAD can route to the GT <RXN1> pin only if the load
   component is placed at an offset of (-2, -1) with respect to the driver
   component. This placement is UNROUTABLE in PAR and therefore, this error
   condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
   < PIN "plbv46_pcie_0_RXN_pin_1_IBUF.O" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN
   "plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i.RXN1" CLOCK_DEDICATED_ROUTE =
   FALSE; >
ERROR:Place:1040 - Unroutable Placement! An IPAD / GT component pair have been
   found that are not placed at a routable IPAD / GT site pair. The IPAD
   component <plbv46_pcie_0_RXP_pin<0>> is placed at site <IPAD_X1Y7>. The
   corresponding GT component
   <plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i> is placed at site
   <GTX_DUAL_X0Y3>. The IPAD can route to the GT <RXP0> pin only if the load
   component is placed at an offset of (-2, -2) with respect to the driver
   component. This placement is UNROUTABLE in PAR and therefore, this error
   condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
   < PIN "plbv46_pcie_0_RXP_pin_0_IBUF.O" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN
   "plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i.RXP0" CLOCK_DEDICATED_ROUTE =
   FALSE; >
ERROR:Place:1036 - Unroutable Placement! An IPAD / GT component pair have been
   found that are not placed at a routable IPAD / GT site pair. The IPAD
   component <plbv46_pcie_0_RXN_pin<0>> is placed at site <IPAD_X1Y6>. The
   corresponding GT component
   <plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i> is placed at site
   <GTX_DUAL_X0Y3>. The IPAD can route to the GT <RXN0> pin only if the load
   component is placed at an offset of (-2, 1) with respect to the driver
   component. This placement is UNROUTABLE in PAR and therefore, this error
   condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
   < PIN "plbv46_pcie_0_RXN_pin_0_IBUF.O" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN
   "plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i.RXN0" CLOCK_DEDICATED_ROUTE =
   FALSE; >

В ucf файле:

Код

Net plbv46_pcie_0_RXN_pin<0> LOC=T1;
Net plbv46_pcie_0_RXN_pin<0> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXN_pin<1> LOC=U1;
Net plbv46_pcie_0_RXN_pin<1> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXN_pin<2> LOC=K1;
Net plbv46_pcie_0_RXN_pin<2> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXN_pin<3> LOC=L1;
Net plbv46_pcie_0_RXN_pin<3> IOSTANDARD = LVDS_25;

Net plbv46_pcie_0_RXP_pin<0> LOC=R1;
Net plbv46_pcie_0_RXP_pin<0> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXP_pin<1> LOC=V1;
Net plbv46_pcie_0_RXP_pin<1> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXP_pin<2> LOC=J1;
Net plbv46_pcie_0_RXP_pin<2> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXP_pin<3> LOC=M1;
Net plbv46_pcie_0_RXP_pin<3> IOSTANDARD = LVDS_25;

Net plbv46_pcie_0_TXN_pin<0> LOC=C2;
Net plbv46_pcie_0_TXN_pin<0> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXN_pin<1> LOC=F2;
Net plbv46_pcie_0_TXN_pin<1> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXN_pin<2> LOC=J2;
Net plbv46_pcie_0_TXN_pin<2> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXN_pin<3> LOC=M2;
Net plbv46_pcie_0_TXN_pin<3> IOSTANDARD = LVDS_25;

Net plbv46_pcie_0_TXP_pin<0> LOC=B2;
Net plbv46_pcie_0_TXP_pin<0> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXP_pin<1> LOC=G2;
Net plbv46_pcie_0_TXP_pin<1> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXP_pin<2> LOC=H2;
Net plbv46_pcie_0_TXP_pin<2> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXP_pin<3> LOC=N2;
Net plbv46_pcie_0_TXP_pin<3> IOSTANDARD = LVDS_25;

Подключил 112 и 116 MGT к 4-lane PCIe.

Объясните, пожалуйста, нужно было выбрать другие MGT?
В чем суть ошибки и можно ли её как-нибудь обойти.
Я пока только могу предположить использование в режиме 1-lane .