ERC32 в Quartus Опции

[g-coder]

Уважаемые форумчане! Помогите скомпилировать процессор ERC32 в Quartus II.
При компилировании выскакивает ошибка:

Код

Error (10559): VHDL Subprogram Call error at iurt_lib.vhd(208): actual for formal parameter "DelayedData" must be a "signal"

Код

  SigRESET_N  : SetupHoldCheck(RESET_N, CLK, EDGE => RISING,
                               SETUP => tRS,  HOLD => tRH,
                               PATH => "RESET_N",
                               DelayedData => RESET_N'DELAYED(abs(tRH)));

Вот описание процедуры:

Код

    -----------------------------------------------------------
    -- Procedure Name : SetupHoldCheck
    -- Purpose : Check of setup-hold condition
    --  must be called concurrently (lasts Infinitely)
    --     Negative values accepted
    --     Verifies that the data does not change during the setup-hold interval
    --     The data is not allowed to change at the edge of the interval
    --     A 0-value for both edges produces no check
    --  The data is delayed at calling, since it is impossible in a procedure
    --  Beware that HOLD >= Tcycle leads to an incorrect behavior
    --
    -- Use (general form) :    
    --     SetupHoldCheck(    Data => Data,
    --                             Ref => Clk,
    --                             EDGE => FALLING,
    --                          SETUP => TSU, HOLD => THO,
    --                           PATH => "SEQUENCER/REG",
    --                                    DelayedData => Data'delayed(abs(HOLD)));
    --
    -----------------------------------------------------------
    procedure SetupHoldCheck (
        signal Data : std_ulogic;    -- as a subtype works for std_logic as well
        signal Ref : std_ulogic;
        constant EDGE : edge_type := RISING;
        constant SETUP, HOLD : time := 0 ns;
        constant PATH : string := "";
        signal DelayedData : std_ulogic);
            -- DelayedData must be set to Data'Delayed(abs(HOLD))
            --  for negative hold processing
    
    procedure SetupHoldCheck (
        signal Data : std_ulogic_vector;    
        signal Ref : std_ulogic;
        constant EDGE : edge_type := RISING;
        constant SETUP, HOLD : time := 0 ns;
        constant PATH : string := "";
        signal DelayedData : std_ulogic_vector);
            -- DelayedData must be set to Data'Delayed(abs(HOLD))
            --  for negative hold processing
    
    procedure SetupHoldCheck (
        signal Data : std_logic_vector;    -- not a subtype of std_ulogic_vector
        signal Ref : std_ulogic;
        constant EDGE : edge_type := RISING;
        constant SETUP, HOLD : time := 0 ns;
        constant PATH : string := "";
        signal DelayedData : std_logic_vector);
            -- DelayedData must be set to Data'Delayed(abs(HOLD))
            --  for negative hold processing
    
    -----------------------------------------------------------