Проект EDK 14.2 c CAN не проходит PAR из-за проблем с CLK, Xilinx Spartan3 Опции

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Здравствуйте, уважаемые форумчане!

Создал проект EDK 14.2 на SPARTAN3A-DSP. В проекте есть Microblaze, DDR, TEMAC, IIC, SPI. Все было ОК.
Начал добавлять CAN. Ему нужен отдельный CLK. Выставил=12.5МГц, исходя из требуемой скорости обмена по CAN. Дополнительный CLK добавил в clock_generator. PAR выдает ошибку:

Код

[Place 1012] A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair.  The clock component <clock_generator_0/clock_generator_0/DCM1_INST/Using_Virtex.DCM_INST/DCM_SP> is placed at site <DCM_X2Y3>.  The clock IO/DCM site can be paired if they are placed/locked in the same quadrant.  The IO component <sys_clk_pin> is placed at site <G13>.  This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule.
< NET "sys_clk_pin" CLOCK_DEDICATED_ROUTE = FALSE; >
< PIN "clock_generator_0/clock_generator_0/DCM1_INST/Using_Virtex.DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; >

После CLOCK_DEDICATED_ROUTE = FALSE все, конечно, заработало, но душа не лежит.

Подскажите, можно ли обойтись без CLOCK_DEDICATED_ROUTE.

Заранее благодарен!