Создание блока памяти RAM в ПЛИС, Нужно оптимизировать Опции

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Здравствуйте!
Пишу на ПЛИС блок памяти 16 ячеек по 16 бит (камень - epm570). От обычного (мегафункция "single 1-RAM PORT") отличается лишь тем, что имеет выходы данных по всем адресам (на рисунке обозначены как data_out1...data_out16).

Вот описание этого элемента:

Код

-- Quartus II VHDL Template

library ieee;
use ieee.std_logic_1164.all;

entity RAM_16x16 is

    port
    (
        adr             : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        data_in        : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
        wren        : in std_logic;
        clk              : in std_logic;
        
        data_cur    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);    --текущие данные
        data_out1    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);    --данные 1
        data_out2    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);    --данные 2
        data_out3    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        data_out4    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        data_out5    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        data_out6    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        data_out7    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        data_out8    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        data_out9    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        data_out10    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        data_out11    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        data_out12    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        data_out13    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        data_out14    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        data_out15    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        data_out16    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)    --данные 16
    );

end entity;

architecture a_RAM_16x16 of RAM_16x16 is
    
    --регистры хранения данных
    SIGNAL data_1    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_2    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_3    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_4    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_5    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_6    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_7    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_8    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_9    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_10    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_11    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_12    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_13    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_14    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_15    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL data_16    : STD_LOGIC_VECTOR (15 DOWNTO 0);
    
begin

    process (clk)
    begin
        if (rising_edge(clk)) then
            if (wren='1') then
                
                case adr is
                when "0000" =>
                    data_1 <= data_in;
                    data_out1<=data_in;
                when "0001" =>
                    data_2 <= data_in;
                    data_out2 <= data_in;
                when "0010" =>
                    data_3 <= data_in;
                    data_out3 <= data_in;
                when "0011" =>
                    data_4 <= data_in;    
                    data_out4 <= data_in;
                when "0100" =>
                    data_5 <= data_in;    
                    data_out5 <= data_in;
                when "0101" =>
                    data_6 <= data_in;    
                    data_out6 <= data_in;
                when "0110" =>
                    data_7 <= data_in;    
                    data_out7 <= data_in;
                when "0111" =>
                    data_8 <= data_in;    
                    data_out8 <= data_in;
                when "1000" =>
                    data_9 <= data_in;    
                    data_out9 <= data_in;
                when "1001" =>
                    data_10 <= data_in;    
                    data_out10 <= data_in;
                when "1010" =>
                    data_11 <= data_in;    
                    data_out11 <= data_in;
                when "1011" =>
                    data_12 <= data_in;    
                    data_out12 <= data_in;
                when "1100" =>
                    data_13 <= data_in;    
                    data_out13 <= data_in;
                when "1101" =>
                    data_14 <= data_in;    
                    data_out14 <= data_in;
                when "1110" =>
                    data_15 <= data_in;    
                    data_out15 <= data_in;
                when "1111" =>
                    data_16 <= data_in;    
                    data_out16 <= data_in;

                end case;
            
            else
                
                case adr is
                when "0000" =>
                    data_cur <= data_1;
                when "0001" =>
                    data_cur <= data_2;
                when "0010" =>
                    data_cur <= data_3;
                when "0011" =>
                    data_cur <= data_4;    
                when "0100" =>
                    data_cur <= data_5;    
                when "0101" =>
                    data_cur <= data_6;    
                when "0110" =>
                    data_cur <= data_7;
                when "0111" =>
                    data_cur <= data_8;
                when "1000" =>
                    data_cur <= data_9;
                when "1001" =>
                    data_cur <= data_10;
                when "1010" =>
                    data_cur <= data_11;
                when "1011" =>
                    data_cur <= data_12;
                when "1100" =>
                    data_cur <= data_13;
                when "1101" =>
                    data_cur <= data_14;
                when "1110" =>
                    data_cur <= data_15;
                when "1111" =>
                    data_cur <= data_16;                
                end case;
                
            end if;
        end if;
    end process;

end a_RAM_16x16;

После компиляции этот блок занимает больше половины ресурсов ПЛИС.
Уважаемые гуру ПЛИС - можно ли оптимизировать этот код?

Извиняюсь за создание темы не по адресу. Вопрос перенесен сюда
Прошу модератора удалить тему из этого раздела.