Появились вакансии инженеров-топологов, Работа в Taipei, Taiwan Опции

[chronos]

В дизайн-центр в Тайбэе( Тайвань) требуются инженеры-топологи .
Description 1. Physical design, including
(1) Fully custom layout with Virtuoso (Cadence)
(2) Auto placement and routing(APR) with IC Compiler (Synopsys)
2. Physical verification (LVS, ERC and DRC) of completed designs and independently debugs and fixes issues with Calibre (Mentor Graphics).
3. Understanding development requirements, and develop schedules with project manager and layout leads
4. Prepare documents for chip sign-off procedure
5. Support foundry Job deck view (JDV) after sign-off procedure
6. Organize layout issues into guideline documents

Requirements Minimum qualification
1. BS/MS degree in EE, CS field
2. Concepts in IC process, design flow
3. Understand the basic circuit architecture and characteristics
4. Familiar with layout EDA tool (Virtuoso - Cadence)
5. Familiar with layout verification tool (Calibre - Mentor Graphics)
6. Language: English (limited working proficiency)
Preferred qualification
7. Familiar with APR tool (IC Compiler – Synopsys)
8. Familiar with UNIX operation, and scripting language (shell script, perl, skill…etc)
9. Good knowledge in mixed-signal circuit layout, such as device matching, noise coupling, ESD and latch-up …etc
10. Good communication skill, and team work ability

Предложение достаточно гибкое, удаленная работа исключена. Китайцев впечатляет работа постсоветских инженеров, хотят расширить штат.

Как вариант , компания проставляет перелет, несколько месяцев испытательный срок. Если не срослось, то билет назад тоже за счет компании.

Уточняющие вопросы или резюме можно слать на chronos18@yandex.ru