Ошибка в Concept-HDL Опции

[rifch]

Здравствуйте у меня вот такой вопрос.
Как бороться с такой ошибкой и от чего она возникает?


Reading Configuration: test_lib t1 cfg_package


Calling HDLDirect with lib.cell:view test_lib.t1:sch_1

*********************************************************************
Netlisting Errors : 1
Netlisting Warnings : 0
*********************************************************************

HDL Direct 15.70-s001 9-Nov-2006
Copyright © 1996 Cadence Design Systems, Inc.

Processing cell view: t1(SCH_1)

Generating for languages: Verilog
Processing page 1
Total number of pages: 1


Generating Output File lib.cell:view test_lib.t1:sch_1


Verilog-Analyzer reports error on test_lib.t1(sch_1). Please check the log file: temp/van.log.

Error #272: 272: Failed to analyze. Please check the log file
for details.
Verilog-Analyzer reports error on test_lib.t1(sch_1). Please check the log file: temp/van.log.
Error in HDL Direct: Verilog-Analyzer reports error on test_lib.t1(sch_1). Please check the log file: temp/van.log.

Exiting due to errors.


*********************************************************************
Total Netlisting Errors : 1
Total Netlisting Warnings : 0
Error (Log) File : temp/netassembler.log


а это файл van.log

VAN 05.01-s01 running at Jun 21, 2007 20:24:25
Copyright Cadence Design Systems, Inc. 2000, 2002
Compiling source file "D:\CADENCE\WORK\test_archive\worklib\t1\sch_1\verilog.v"
Reading globals package test_lib.glbl:t1_cfg_package
Writing test_lib.t1:sch_1