CADSTAR FPGA / ALDEC Active HDL Webinar Webinar, Oct 16 2008 Опции

[Yuri Potapoff]

CADSTAR FPGA / ALDEC Active HDL Webinar Webinar

Oct 16 2008

Webinar - 3.00pm (CEST - central European summer time)

Synchronization for Smooth Integration of PCB and FPGA Development Environments

Aldec and Zuken developed a smooth synchronization between Aldec Active-HDL/CADSTAR FPGA and Zuken CADSTAR SCM/PCB offering complete support for all FPGA vendors from design creation to mixed VHDL and Verilog simulation, project management, schematic and PCB layout. This seminar includes a design demonstration and presentation on how to use Aldec Active HDL /CADSTAR FPGA and Zuken CADSTAR SCM/PCB in a unified environment.

Agenda:

Introduction
FPGA-PCB Concurrent design flow
Aldec for complete FPGA design and verification
CADSTAR for complete PCB layout and design
Pin file Integration
Design Demonstration

Регистрация