Test Bench + ModelSim Опции

[zorromen]

Привет всем. Пишу переферию на проц, надо проверить его работу. Написал тест бенч, моделирую на modelSim из Quartus. Кргда была простая логика все моделировалось, но когда добавились елементы типа fifo и счетчиков из мегафункций, то моделсим начал ругаться. Походу ему чемто не нравится defparam. Как это симулировать.

143 defparam the_dcfifo.LPM_NUMWORDS = 2048,
144 the_dcfifo.LPM_SHOWAHEAD = "ON",
145 the_dcfifo.LPM_WIDTH = 32;

# Top level modules:
# restore
#
# vlog -vlog01compat -work work +incdir+C:/altera/restore_verilog {C:/altera/restore_verilog/vga_controller_classic_my.v}
# Model Technology ModelSim ALTERA vlog 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Compiling module vga_controller_classic_0
#
# Top level modules:
# vga_controller_classic_0
# vlog -vlog01compat -work work +incdir+C:/altera/restore_verilog {C:/altera/restore_verilog/avalon_master_model.v}
# Model Technology ModelSim ALTERA vlog 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Compiling module avalon_master_model
#
# Top level modules:
# avalon_master_model
# vlog -vlog01compat -work work +incdir+C:/altera/restore_verilog {C:/altera/restore_verilog/my_tb.v}
# Model Technology ModelSim ALTERA vlog 6.3g_p1 Compiler 2008.08 Aug 13 2008
# -- Compiling module my_tb
#
# Top level modules:
# my_tb
#
# vsim -t 1ps -L lpm_ver -L altera_ver -L altera_mf_ver -L sgate_ver -L cycloneii_ver -L rtl_work -L work -voptargs="+acc" my_tb
# vsim -L lpm_ver -L altera_ver -L altera_mf_ver -L sgate_ver -L cycloneii_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps my_tb
# Loading work.my_tb
# Loading work.avalon_master_model
# Loading work.vga_controller_classic_0
# Loading altera_mf_ver.dcfifo
# Loading altera_mf_ver.dcfifo_mixed_widths
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.dcfifo_sync
# Loading altera_mf_ver.dcfifo_dffpipe
# Loading altera_mf_ver.dcfifo_async
# Loading altera_mf_ver.dcfifo_fefifo
# Loading altera_mf_ver.dcfifo_low_latency
# Loading altera_mf_ver.ALTERA_MF_HINT_EVALUATION
# Loading lpm_ver.lpm_counter
# Loading lpm_ver.lpm_shiftreg
# ** Error: (vsim-3043) C:/altera/restore_verilog/vga_controller_classic_my.v(143): Unresolved reference to 'LPM_NUMWORDS' in the_dcfifo.LPM_NUMWORDS.
# Region: /my_tb/u1
# ** Error: (vsim-3043) C:/altera/restore_verilog/vga_controller_classic_my.v(144): Unresolved reference to 'LPM_SHOWAHEAD' in the_dcfifo.LPM_SHOWAHEAD.
# Region: /my_tb/u1
# ** Error: (vsim-3043) C:/altera/restore_verilog/vga_controller_classic_my.v(145): Unresolved reference to 'LPM_WIDTH' in the_dcfifo.LPM_WIDTH.
# Region: /my_tb/u1
# ** Error: (vsim-3043) C:/altera/restore_verilog/vga_controller_classic_my.v(195): Unresolved reference to 'LPM_WIDTH' in dma_address_counter.LPM_WIDTH.
# Region: /my_tb/u1
# ** Error: (vsim-3043) C:/altera/restore_verilog/vga_controller_classic_my.v(218): Unresolved reference to 'LPM_MODULUS' in vga_column_counter.LPM_MODULUS.
# Region: /my_tb/u1
# ** Error: (vsim-3043) C:/altera/restore_verilog/vga_controller_classic_my.v(219): Unresolved reference to 'LPM_WIDTH' in vga_column_counter.LPM_WIDTH.
# Region: /my_tb/u1
# ** Error: (vsim-3043) C:/altera/restore_verilog/vga_controller_classic_my.v(230): Unresolved reference to 'LPM_MODULUS' in vga_row_counter.LPM_MODULUS.
# Region: /my_tb/u1
# ** Error: (vsim-3043) C:/altera/restore_verilog/vga_controller_classic_my.v(231): Unresolved reference to 'LPM_WIDTH' in vga_row_counter.LPM_WIDTH.
# Region: /my_tb/u1
# ** Error: (vsim-3043) C:/altera/restore_verilog/vga_controller_classic_my.v(251): Unresolved reference to 'LPM_WIDTH' in vga_config_counter.LPM_WIDTH.
# Region: /my_tb/u1
# ** Error: (vsim-3043) C:/altera/restore_verilog/vga_controller_classic_my.v(394): Unresolved reference to 'LPM_WIDTH' in vsync_delay.LPM_WIDTH.
# Region: /my_tb/u1
# ** Error: (vsim-3043) C:/altera/restore_verilog/vga_controller_classic_my.v(414): Unresolved reference to 'LPM_WIDTH' in hsync_delay.LPM_WIDTH.
# Region: /my_tb/u1
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./restore_run_msim_rtl_verilog.do PAUSED at line 14