Translate в Xilinx, Непонятные ошибки Опции

[Angel]

В тексте программы есть такие строчки:
N_LRE1 <= '0';
N_LRE2 <= '0';

Вроде бы все просто, но транслятор Xilinx-а выдает непонятно что:
Checking expanded design ...
ERROR:NgdBuild:455 - logical net 'N_LRE2_OBUF' has multiple drivers. The
possible drivers causing this are:
pin G on block XST_GND with type GND,
pin PAD on block U2/N_LRE2_OBUF with type PAD
ERROR:NgdBuild:462 - input pad net 'N_LRE2_OBUF' drives multiple buffers.
Possible pins causing this are: :
pin I on block N_LRE1_OBUF with type OBUF,
pin I on block N_LRE2_OBUF with type OBUF,
pin I on block U2/rstpad with type IBUF
ERROR:NgdBuild:466 - input pad net 'N_LRE2_OBUF' has illegal connection.
Possible pins causing this are:
pin G on block XST_GND with type GND
ERROR:NgdBuild:466 - input pad net 'N_LRE2_OBUF' has illegal connection.
Possible pins causing this are:
pin G on block XST_GND with type GND
ERROR:NgdBuild:466 - output pad net 'lock' has illegal connection. Possible pins
causing this are:
pin I1 on block res/_n00001 with type LUT2

Кто может обьяснить в чем проблема?