//объявление буферов на прием и передачу
uint8_t ow_rx[8];
uint8_t ow_tx[8];

//Частота для dma1
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);

...

DMA_InitTypeDef DMA_InitStructure;
//RX DMA reset
DMA_DeInit(DMA1_Stream5); //For STM32F4
while (DMA_GetCmdStatus(DMA1_Stream5) != DISABLE) {}

//DMA config DMA1, Channel 4, Stream 5: USART2_RX
DMA_InitStructure.DMA_Channel = DMA_Channel_4; //For STM32F4
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(USART2->DR);
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) ow_rx;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
DMA_InitStructure.DMA_BufferSize = num_bytes;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_Init(DMA1_Stream5, &DMA_InitStructure);

//TX DMA reset
DMA_DeInit(DMA1_Stream6); //For STM32F4
while (DMA_GetCmdStatus(DMA1_Stream6) != DISABLE) {}

//DMA config DMA1, Channel 4, Stream 6: USART2_TX
DMA_InitStructure.DMA_Channel = DMA_Channel_4; //For STM32F4
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(USART2->DR);
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) ow_tx;
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
DMA_InitStructure.DMA_BufferSize = num_bytes;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_Init(DMA1_Stream6, &DMA_InitStructure);

//чистим буфер, флаги, и запускаем
USART_ReceiveData(USART2); //clear RX Buffer
USART_ClearFlag(USART2, USART_FLAG_RXNE | USART_FLAG_TC | USART_FLAG_TXE);
USART_DMACmd(USART2, USART_DMAReq_Tx | USART_DMAReq_Rx, ENABLE);
DMA_Cmd(DMA1_Stream5, ENABLE);
DMA_Cmd(DMA1_Stream6, ENABLE);

// Ставим системный таймаут, ждем выхода из дма
OW_TimeOut = ((uint32_t)0x100);
while ((DMA_GetFlagStatus(DMA1_Stream5, DMA_FLAG_TCIF4 | DMA_FLAG_HTIF4 | DMA_FLAG_TEIF4 |
DMA_FLAG_DMEIF4 | DMA_FLAG_FEIF4) == RESET) && (OW_TimeOut != 0)) {
}
if(OW_TimeOut == 0) printf("\r\n DMA Timed Out, ERROR"); //debug
if((DMA_GetFlagStatus(DMA1_Stream5, DMA_FLAG_TEIF4) == SET)) printf("\r\n Streamx transfer complete flag"); //debug
if((DMA_GetFlagStatus(DMA1_Stream5, DMA_FLAG_HTIF4) == SET)) printf("\r\n half transfer complete flag"); //debug
if((DMA_GetFlagStatus(DMA1_Stream5, DMA_FLAG_TEIF4) == SET)) printf("\r\n transfer error flag"); //debug
if((DMA_GetFlagStatus(DMA1_Stream5, DMA_FLAG_DMEIF4) == SET)) printf("\r\n direct mode error flag"); //debug
if((DMA_GetFlagStatus(DMA1_Stream5, DMA_FLAG_FEIF4) == SET)) printf("\r\n FIFO error flag"); //debug

// disable DMA
DMA_Cmd(DMA1_Stream6, DISABLE);
DMA_Cmd(DMA1_Stream5, DISABLE);
USART_DMACmd(USART2, USART_DMAReq_Tx | USART_DMAReq_Rx, DISABLE);