Наткнулся на такое: есть проект, компилирую с нуля, запускаю EDA gate level simulation - все ровно, рисует как надо. Добавляю компонент altdq (параметры на рисунках), до этого в проекте такого компонента не было. Запускаю тот же EDA gate level simulation - пишет следующее (вытащил кусок лога):
Код
Loading work.fourier_tbbb
# Loading work.soft_ldpc_st2
# Loading cycloneiii_ver.cycloneiii_pll
# Loading cycloneiii_ver.cycloneiii_m_cntr
# Loading cycloneiii_ver.cycloneiii_n_cntr
# Loading cycloneiii_ver.cycloneiii_scale_cntr
# Loading altera_ver.dffeas
# Loading cycloneiii_ver.cycloneiii_lcell_comb
# Loading cycloneiii_ver.cycloneiii_clkctrl
# Loading cycloneiii_ver.cycloneiii_mux41
# Loading cycloneiii_ver.cycloneiii_ena_reg
# Loading cycloneiii_ver.cycloneiii_io_obuf
# Loading cycloneiii_ver.cycloneiii_io_ibuf
# Loading cycloneiii_ver.cycloneiii_ram_block
# Loading cycloneiii_ver.cycloneiii_ram_register
# Loading cycloneiii_ver.cycloneiii_ram_pulse_generator
# Loading cycloneiii_ver.cycloneiii_ddio_out
# Loading cycloneiii_ver.cycloneiii_latch
# Loading cycloneiii_ver.cycloneiii_mux21
# SDF 6.5b Compiler 2009.10 Oct 1 2009
#
# Loading instances from test3c40_8_1200mv_85c_v_slow.sdo
# Loading altera_ver.PRIM_GDFF_LOW
# Loading timing data from test3c40_8_1200mv_85c_v_slow.sdo
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
# File in use by: Пользователь Hostname: ALEXPC ProcessID: 4936
# Attempting to use alternate WLF file "./wlftnniha9".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
# Using alternate file: ./wlftnniha9
# ** Error: (vsim-SDF-3261) test3c40_8_1200mv_85c_v_slow.sdo(23033): Failed to find matching specify module path.
# ** Error: (vsim-SDF-3262) test3c40_8_1200mv_85c_v_slow.sdo(23037): Failed to find matching specify timing constraint.
# ** Fatal: (vsim-SDF-3444) Failed to annotate from SDF file "test3c40_8_1200mv_85c_v_slow.sdo".
# Time: 0 ps Iteration: 0 Instance: /fourier_tbbb File: D:/altera_proj/softldpc_st2/3c40_admtv803/simulation/modelsim/softldpc_tb_st2.v
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./test3c40_run_msim_gate_verilog.do PAUSED at line 12
# Loading work.soft_ldpc_st2
# Loading cycloneiii_ver.cycloneiii_pll
# Loading cycloneiii_ver.cycloneiii_m_cntr
# Loading cycloneiii_ver.cycloneiii_n_cntr
# Loading cycloneiii_ver.cycloneiii_scale_cntr
# Loading altera_ver.dffeas
# Loading cycloneiii_ver.cycloneiii_lcell_comb
# Loading cycloneiii_ver.cycloneiii_clkctrl
# Loading cycloneiii_ver.cycloneiii_mux41
# Loading cycloneiii_ver.cycloneiii_ena_reg
# Loading cycloneiii_ver.cycloneiii_io_obuf
# Loading cycloneiii_ver.cycloneiii_io_ibuf
# Loading cycloneiii_ver.cycloneiii_ram_block
# Loading cycloneiii_ver.cycloneiii_ram_register
# Loading cycloneiii_ver.cycloneiii_ram_pulse_generator
# Loading cycloneiii_ver.cycloneiii_ddio_out
# Loading cycloneiii_ver.cycloneiii_latch
# Loading cycloneiii_ver.cycloneiii_mux21
# SDF 6.5b Compiler 2009.10 Oct 1 2009
#
# Loading instances from test3c40_8_1200mv_85c_v_slow.sdo
# Loading altera_ver.PRIM_GDFF_LOW
# Loading timing data from test3c40_8_1200mv_85c_v_slow.sdo
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
# File in use by: Пользователь Hostname: ALEXPC ProcessID: 4936
# Attempting to use alternate WLF file "./wlftnniha9".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
# Using alternate file: ./wlftnniha9
# ** Error: (vsim-SDF-3261) test3c40_8_1200mv_85c_v_slow.sdo(23033): Failed to find matching specify module path.
# ** Error: (vsim-SDF-3262) test3c40_8_1200mv_85c_v_slow.sdo(23037): Failed to find matching specify timing constraint.
# ** Fatal: (vsim-SDF-3444) Failed to annotate from SDF file "test3c40_8_1200mv_85c_v_slow.sdo".
# Time: 0 ps Iteration: 0 Instance: /fourier_tbbb File: D:/altera_proj/softldpc_st2/3c40_admtv803/simulation/modelsim/softldpc_tb_st2.v
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./test3c40_run_msim_gate_verilog.do PAUSED at line 12
Убираю поставленный компонент altdq, больше ничего не меняю - и опять все нормально симулируется.
Делаю вывод: не хочет моделсим симулировать altdq. При этом в логе есть такая строчка: "Loading cycloneiii_ver.cycloneiii_ddio_out"
Компиляция в обоих случаях проходит нормально, без каких-то ворнингов и даже намеков в сторону симуляции.
Как его заставить, кто-то сталкивался?
Квартус 9.1 sp2, modelsim altera 6.5b. До сих пор проблем ни с квартусом, ни с моделсимом не было...
