reg [31:0] av_address;
reg [31:0] av_wr_data;
reg av_write;
reg av_read;
reg av_wait_req;


assign DRAM_CLK = CLOCK_50;

//=======================================================
// Structural coding
//=======================================================

my_sdram (
// 1) global signals:
.clk_0(CLOCK_50),
.clk_0_reset(),
.reset_n(KEY[0]),

// the_my_master_0_avalon_master
.address_from_the_my_master_0(av_address),
.rd_data_to_the_my_master_0(LEDG),
.rd_data_valid_to_the_my_master_0(),
.read_from_the_my_master_0(av_read),
.wait_req_to_the_my_master_0(av_wait_req),
.wr_data_from_the_my_master_0(av_wr_data),
.write_from_the_my_master_0(av_write),

// the_sdram_0
.zs_addr_from_the_sdram_0(DRAM_ADDR),
.zs_ba_from_the_sdram_0(DRAM_BA),
.zs_cas_n_from_the_sdram_0(DRAM_CAS_N),
.zs_cke_from_the_sdram_0(DRAM_CKE),
.zs_cs_n_from_the_sdram_0(DRAM_CS_N),
.zs_dq_to_and_from_the_sdram_0(DRAM_DQ),
.zs_dqm_from_the_sdram_0(DRAM_DQM),
.zs_ras_n_from_the_sdram_0(DRAM_RAS_N),
.zs_we_n_from_the_sdram_0(DRAM_WE_N)
)
;

////////////////////////////

always @(posedge CLOCK_50)begin
if(SW[0]) begin
av_address = 32'd115;
av_wr_data = 32'd15;
av_write = 1'b1;
av_read = 1'b0;
end

if(SW[1]) begin
av_address = 32'd215;
av_wr_data = 32'd240;
av_write = 1'b1;
av_read = 1'b0;
end

if(SW[5]) begin
av_address = 32'd115;
av_write = 1'b0;
av_read = 1'b1;
end

if(SW[6]) begin
av_address = 32'd215;
av_write = 1'b0;
av_read = 1'b1;
end

end