library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity main is
    Port ( clk_i : in  STD_LOGIC;
              clk_out : out  STD_LOGIC;  // Вход 50 MHZ
              clk_fx : out  STD_LOGIC;    // Выход умноженой частоты
              res_o : out  STD_LOGIC;     // Значение сигнала сброса
           ledout1 : out  STD_LOGIC_VECTOR(7 downto 0));  // Выходы на СД
end main;

architecture Behavioral of main is
    COMPONENT d2
    PORT(
        CLKIN_IN : IN std_logic;
        RST_IN : IN std_logic;          
        CLKFX_OUT : OUT std_logic;
        CLKIN_IBUFG_OUT : OUT std_logic;
        CLK0_OUT : OUT std_logic;
        CLK2X180_OUT : OUT std_logic
        );
    END COMPONENT;

signal CLK0_OUT : std_logic;
signal LOCKED_OUT : std_logic;    
signal USER_RST_IN : std_logic;
signal clk_o : std_logic;
signal led_i :  STD_LOGIC_VECTOR(7 downto 0) := "00000001";
signal clk_v: std_logic;
begin
    Inst_d2: d2 PORT MAP(
        CLKIN_IN => clk_i,
        RST_IN => USER_RST_IN ,
        CLKFX_OUT => clk_v,
        CLKIN_IBUFG_OUT => clk_o ,
        CLK0_OUT => CLK0_OUT,
        CLK2X180_OUT => LOCKED_OUT
    );
    
process ( clk_v)
variable count : std_logic_vector ( 20 downto 0 ) := (others => '0');
begin
    if (clk_v'event and clk_v = '1' ) then
        if count = "111111111111111111111" then
            count := "000000000000000000000";
            led_i <= led_i + 1;
        else
            count := count + 1;
        end if;
    end if;
end process;

process ( clk_o)
variable count : std_logic_vector ( 7 downto 0 ) := (others => '1');
begin
    if (clk_o'event and clk_o = '1' ) then
        if count = 0 then
            USER_RST_IN <= '0';
        else
            count := count - 1;
            USER_RST_IN <= '1';
        end if;
    end if;
end process;

ledout1 <= led_i;
res_o <= USER_RST_IN;
clk_out <= clk_o;
clk_fx <= clk_v;

end Behavioral;