#define SDRAM_BASE 0xA0000000
#define SDRAM_SIZE 0x4000000


#define tCLK_ns (double)((double)120000000 / 1000000000.0 ) // CCLK period in ns
#define NS_2_CLKS(ns) ( (uint32_t)( (double)(ns) * tCLK_ns ) + 1 ) // convert ns to CCLKs


uint8_t sdram_test(void)
{
uint32_t i;
uint16_t* adr_ptr = (uint16_t*)SDRAM_BASE+0x38;
uint16_t temp;
uint32_t test = 1; // 0 - error, 1 - successfull test
Writing in the SDRAM
for(i = 0; i<SDRAM_SIZE/16;i++)
{
*adr_ptr++ = 0x1234;
}
//Reading SDRAM
adr_ptr = (uint16_t*)SDRAM_BASE+0x38;
for(i = 0; i<SDRAM_SIZE/16;i++)
{
temp = *adr_ptr;

if (temp!=0x1234)
test = 0;
adr_ptr++;
}
return test;
}
void init_EMC_and_SDRAM(void)
{
uint32_t temp;
//
//EMC initialization
//
LPC_SC->SCS &= ~(1<<1); //EMC reset when any resert occures
LPC_SC->PCONP |= 1<<11; //Power of EMC

LPC_IOCON->P2_16 = 1; //P2.16 - CAS
LPC_IOCON->P2_17 = 1; //P2.17 - RAS
LPC_IOCON->P2_18 = 1; //P2.18 - CLK
LPC_IOCON->P2_20 = 1; //P2.20 - CS
LPC_IOCON->P2_24 = 1; //P2.24 - CKE
LPC_IOCON->P2_28 = 1; //P2.28 - DQML
LPC_IOCON->P2_29 = 1; //P2.29 - DQMH

LPC_IOCON->P4_1 = 1; //P4.1 - A0
LPC_IOCON->P4_2 = 1; //P4.2 - A1
LPC_IOCON->P4_3 = 1; //P4.3 - A2
LPC_IOCON->P4_4 = 1; //P4.4 - A3
LPC_IOCON->P4_5 = 1; //P4.5 - A4
LPC_IOCON->P4_6 = 1; //P4.6 - A5
LPC_IOCON->P4_7 = 1; //P4.7 - A6
LPC_IOCON->P4_8 = 1; //P4.8 - A7
LPC_IOCON->P4_9 = 1; //P4.9 - A8
LPC_IOCON->P4_10 = 1; //P4.10 - A9
LPC_IOCON->P4_11 = 1; //P4.11 - A10
LPC_IOCON->P4_12 = 1; //P4.12 - A11
LPC_IOCON->P4_13 = 1; //P4.11 - BA0
LPC_IOCON->P4_14 = 1; //P4.12 - BA1

LPC_IOCON->P3_0 = 1; //P3.0 - D0
LPC_IOCON->P3_1 = 1; //P3.1 - D1
LPC_IOCON->P3_2 = 1; //P3.2 - D2
LPC_IOCON->P3_3 = 1; //P3.3 - D3
LPC_IOCON->P3_4 = 1; //P3.4 - D4
LPC_IOCON->P3_5 = 1; //P3.5 - D5
LPC_IOCON->P3_6 = 1; //P3.6 - D6
LPC_IOCON->P3_7 = 1; //P3.7 - D7
LPC_IOCON->P3_8 = 1; //P3.8 - D8
LPC_IOCON->P3_9 = 1; //P3.9 - D9
LPC_IOCON->P3_10 = 1; //P3.10 - D10
LPC_IOCON->P3_11 = 1; //P3.11 - D11
LPC_IOCON->P3_12 = 1; //P3.12 - D12
LPC_IOCON->P3_13 = 1; //P3.13 - D13
LPC_IOCON->P3_14 = 1; //P3.14 - D14
LPC_IOCON->P3_15 = 1; //P3.15 - D15

LPC_SC->EMCCLKSEL = 0x00000000; // EMC uses a clock rate equal to CPU clock rate
LPC_SC->CLKOUTCFG = 0x00000100; // enables clock, sets clock source as CPU clk / 1
LPC_SC->EMCDLYCTL = 0x000000A05;
LPC_EMC->Control = 1; //Enable EMC
LPC_EMC->Config = 0; // little-endian mode, clkout = cclk
LPC_EMC->DynamicReadConfig = 0x00000001; // Command delayed strategy, using EMCCLKDELAY
LPC_EMC->DynamicRasCas0 = 0x0303; //Define RAS and CAS
LPC_EMC->DynamicConfig0 = 0x280; //64 Mb (4Mx16), 4 banks, row length = 12, column length = 8 (Row,Bank,Colum)

LPC_EMC->DynamicRP = NS_2_CLKS(20)-1; // tRP: precharge command period (20ns)
LPC_EMC->DynamicRAS = NS_2_CLKS(44)-1; // tRAS: active to precharge command period (44ns)
LPC_EMC->DynamicSREX = NS_2_CLKS(75)-1; // tXSR: self-refresh exit time (75ns)
LPC_EMC->DynamicAPR = NS_2_CLKS(20)-1; // tAPR: last-data-out to active command time
// note: no tAPR value, using tRCD value (20ns)
LPC_EMC->DynamicDAL = 5; // tDAL: data-in to active command time
// for CL=3, tDAL = 5 tCK
// for CL=2, tDAL = 4 tCK
// for CL=1, tDAL = 3 tCK
LPC_EMC->DynamicWR = (NS_2_CLKS(7.5)+1)-1; //LPC_EMC->DynamicWR = (NS_2_CLKS(7.5)+1); // tWR: write recovery time is (15ns) UNLESS we're
// using AUTO PRECHARGE, then it's (tCK+7.5ns)
LPC_EMC->DynamicRC = NS_2_CLKS(66)-1; // tRC: ACTIVE-to-ACTIVE command period (66ns)
LPC_EMC->DynamicRFC = NS_2_CLKS(66)-1; // tRFC: AUTO REFRESH period (66ns)
LPC_EMC->DynamicXSR = NS_2_CLKS(75)-1; // tXSR: Exit self refresh to ACTIVE command (75ns)
LPC_EMC->DynamicRRD = NS_2_CLKS(15)-1; // tRRD: active bank A to active bank B command
// latency (15ns)
LPC_EMC->DynamicMRD = 2-1; // tMRD: LOAD MODE REGISTER command to ACTIVE or
// REFRESH command time (2tCK)

//SDRAM initialization
delay_ms(100);//wait 100us after power is enabled
LPC_EMC->DynamicControl = 0x00000183; //SDRAM initialization value to NOP
delay_ms(200); //wait >100us
LPC_EMC->DynamicControl = 0x00000103; //SDRAM initialization value to PAL
LPC_EMC->DynamicRefresh = 0x02; //Refresh
for(temp = 128;temp;temp--)
LPC_EMC->DynamicRefresh = 0x75; //Refresh cycle 15,625 us
for(temp = 128;temp;temp--)
LPC_EMC->DynamicControl = 0x00000083; //SDRAM initialization value to MODE
temp = *((uint32_t *)(SDRAM_BASE|(0x033<<(8+1+2)))); //Programming the MODE register (Row,Bank,Colum)
for(temp = 128;temp;temp--)
LPC_EMC->DynamicControl = 0x00000000; //SDRAM initialization value to NORMAL
LPC_EMC->DynamicConfig0 |= 0x00080000; // Enable buffer
}