случайно нарыл
http://caes.ewi.utwente.nl/index.php/resea...erial/sabrewing
Sabrewing tightly integrates floating-point and integer arithmetic in a single datapath. Because the architecture is mainly intended for use in low-power embedded digital signal processors, the following design constraints where adhered during its implementation: limited use of pipelining for the convenience of the compiler; maintaining compatibility with existing technology for easy integration; minimal area and power consumption for applicability in embedded systems. The architecture is tailored to digital signal processing by combining floating-point fused multiply-add and integer multiply-accumulate. It could be deployed in a multi-core system-on-chip designed to support applications with and without dominance of floating-point calculations.
может кому пригодится хотя и
The VHDL structural description of this architecture is available for download under BSD license