// Трансляция тактирования от кварца на АЦП
OBUFDS    #(.IOSTANDARD("LVDS_25")) lvds_clk_obuf    
(
.I(crystal_clk),      
.O(adc_clkp),         
.OB(adc_clkm)
);

...

// Входной буфер побитового тактирования с АЦП
IBUFGDS    #(.IOSTANDARD("LVDS_25"), .IBUF_DELAY_VALUE("0"), .DIFF_TERM("TRUE")) lvds_bit_clk_ibuf   (.I(adc_bit_clkp), .IB(adc_bit_clkm), .O(bit_clk) );

...

//  Входные буфера данных с АЦП
IBUFDS    #(.IOSTANDARD("LVDS_25"), .IFD_DELAY_VALUE("0"), .DIFF_TERM("TRUE"))  lvds_bit_a0_ibuf   (.I(adc_da0_p), .IB(adc_da0_m), .O(inv_bit_A0) );

...

// Входные DDR регистры данных
IDDR2     
#(.DDR_ALIGNMENT("C0")) fd_io_0 (.C0(rxclk_dcm), .C1(rxclk_dcm_180), .D(inv_bit_A0), .CE(1'b1), .R(1'b0), .S(1'b0), .Q0(data_in_reg_A0[0]), .Q1(data_in_reg_A0[1]));

module adc_deserializer
#(parameter ch_num = 8, ser_factor = 14, invert_input_clock = "OFF")
(
input bit_clk,
input frame_clk,
input reset_n,
input [ch_num-1:0] adc_data_serial,
output reg [ser_factor-1:0] adc_data[ch_num]
);
reg [1:0] frame_clk_reg = '0;
integer n;
always_ff @(posedge bit_clk) begin
frame_clk_reg <= {frame_clk_reg, frame_clk};
end
wire frame_clk_rising_edge = frame_clk_reg[0]&(!frame_clk_reg[1]);
genvar i;
generate
for(i = 0; i < ch_num; i++) begin: lvds_rx
reg [ser_factor-1:0] lvds_sr = '0;
wire dataout_h;
wire dataout_l;
altddio_in altddio_in_inst
(
.aclr(1'b0),
.datain(adc_data_serial[i]),
.inclock(bit_clk),
.dataout_h(dataout_h),
.dataout_l(dataout_l),
.aset(1'b0),
.inclocken(1'b1)
);
defparam
altddio_in_inst.intended_device_family = "Cyclone IV GX",
altddio_in_inst.invert_input_clocks = invert_input_clock,
altddio_in_inst.lpm_hint = "UNUSED",
altddio_in_inst.lpm_type = "altddio_in",
altddio_in_inst.power_up_high = "ON"/*"OFF"*/,
altddio_in_inst.width = 1;
always_ff @(posedge bit_clk) begin
lvds_sr <= {lvds_sr[ser_factor-3:0], dataout_l, dataout_h};
end
always_ff @(posedge bit_clk) begin
if (!reset_n)
adc_data[i] <= '0;
else if (frame_clk_rising_edge)
adc_data[i] <= lvds_sr;
end
end
endgenerate
endmodule