// enable TIM2 interrupt
NVIC->ISER[0] |= 1 << TIM2_IRQn;

// configure TIM2_CH1 for input capture //////////////////////////////////

// enable TIM2 clock
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;

TIM2->CR1 = 0; // turn off TIM2

// set prescaler, 1 count = 840/84MHz = 10us resolution
TIM2->PSC = 840;

TIM2->CCMR1 |=
TIM_CCMR1_CC1S_1 |  // CC1 input, IC1 to TI2
TIM_CCMR1_CC2S_0;   // CC2 input, IC2 to TI2


TIM2->CCER |=
TIM_CCER_CC1E | // enable capture
TIM_CCER_CC1P | // inverted/falling edge for CC1
TIM_CCER_CC2E;  // enable capture [noninverted/rising edge for CC2]


TIM2->SMCR |=
TIM_SMCR_TS_2 | // TI1 Edge Detector, TI1F_ED
TIM_SMCR_TS_1 | // Internal Trigger 2, ITR2
TIM_SMCR_SMS_2; // reset mode

TIM2->DIER |=
//TIM_DIER_CC1IE | // CC1 interrupt enable
TIM_DIER_CC2IE;  // CC2 interrupt enable


TIM2->CR1 |=
TIM_CR1_CEN;     // enable TIM2

// enable TIM4 interrupt
NVIC->ISER[0] |= 1 << TIM4_IRQn;
// configure TIM4_CH1 for input capture //////////////////////////////////

// enable TIM4 clock
RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;

TIM4->CR1 = 0; // turn off TIM1

// set prescaler, 1 count = 840/84MHz = 10us resolution
TIM4->PSC = 840;

TIM4->CCMR2 |=
TIM_CCMR2_CC3S_1 |  // CC3 input, IC1 to TI2
TIM_CCMR2_CC4S_0;   // CC4 input, IC2 to TI2


TIM4->CCER |=
TIM_CCER_CC3E | // enable capture
TIM_CCER_CC3P | // inverted/falling edge for CC3
TIM_CCER_CC4E;  // enable capture [noninverted/rising edge for CC4]


TIM4->SMCR |=
TIM_SMCR_TS_2 | // TI1 Edge Detector, TI1F_ED
TIM_SMCR_TS_1 | // Internal Trigger 2, ITR2
TIM_SMCR_SMS_2; // reset mode

TIM4->DIER =
TIM_DIER_CC3IE | // CC3 interrupt enable
TIM_DIER_CC4IE;  // CC4 interrupt enable


TIM4->CR1 |=
TIM_CR1_CEN;     // enable TIM4

void TIM4_IRQHandler()
{

    static    volatile  ch1_pw=0, ch1_period=0;


if (TIM4->SR&2)
    {
       // ch1_pw=TIM1->CCR1;
       // TIM3->CCR1 = (ir_pulse) * 20;

        ch1_pw = TIM4->CCR3;
        TIM3->CCR1 = (ch1_pw) * 20;

    }


    if(TIM4->SR&4)
    {
        ch1_period=TIM2->CCR4;

    }

    TIM4->SR=0;
}