Пытаюсь запустить таймер по прерыванию процессора MKTL25Z128 (Freescale)
Настраиваю 2 таймера с одинаковыми параметрами - один чтобы генерировал прерывания, второй просто опрашиваю флаг прерывания в основном цикле.
Один таймер управляет красным светодиодном, второй - зелёным.
Результат такой - таймер 0 не работает - нет прерываний, таймер 1 моргает светодиодом. Т.е. от таймера прерывания поступают, но нет входа в обработчик.
Разбираюсь уже 2 дня, перелопатил все примеры - делаю вроде всё как положено, но прерывания нет.
Привожу стартап, файл линкера для IAR, процедуру интсалляции прерывания и сам обработчик прерывания
CODE
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:ROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD __iar_program_start ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete intertrupt
DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete intertrupt
DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete intertrupt
DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete intertrupt
DCD 0 ; 4: Reserved DMA Channel 5 transfer complete intertrupt
DCD FTFA_IRQHandler ; 5: FTFA
DCD PMU_IRQHandler ; 6: Low-voltage detect, low-voltage warning
DCD LLWU_IRQHandler ; 7: Low Leakage Wakeup
DCD I2C0_IRQHandler ; 8: IIC 0 interrupt
DCD I2C1_IRQHandler ; 9: IIC 1 intertrupt
DCD SPI0_IRQHandler ;10: SPI0 intertrupt
DCD SPI1_IRQHandler ;11: SPI1 intertrupt
DCD UART0_IRQHandler ;12: UART 0 status and error intertrupt
DCD UART1_IRQHandler ;13: UART 1 status and error intertrupt
DCD UART2_IRQHandler ;14: UART 2 status and error intertrupt
DCD ADC0_IRQHandler ;15: ADC 0 interrupt
DCD CMP0_IRQHandler ;16: CMP 0 interrupt
DCD TPM0_IRQHandler ;17: TPM 0 interrupt
DCD TPM1_IRQHandler ;18: TPM 1 interrupt
DCD TPM2_IRQHandler ;19: TPM 2 interrupt
DCD RTC_Alarm_IRQHandler ;20: RTC Alarm interrupt
DCD RTC_IRQHandler ;21: RTC Seconds interrupt
DCD PIT_IRQHandler ;22: PIT Single interrupt vector for all channels
DCD 0 ;23: Reserved
DCD USB_OTG_IRQHandler ;24: USB OTG intertrupt
DCD DAC0_IRQHandler ;25: UART 0 status intertrupt
DCD TSI0_IRQHandler ;26: TSI 0 interrupt
DCD MCG_IRQHandler ;27: MCG intertrupt
DCD LPTMR0_IRQHandler ;28: LPTMR0 intertrupt
DCD 0 ;29: Reserved
DCD PORTA_IRQHandler ;30: PORT A interrupt
DCD PORTD_IRQHandler ;31: PORT D interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
PUBWEAK NMI_Handler
PUBWEAK HardFault_Handler
PUBWEAK SVC_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK DMA0_IRQHandler
PUBWEAK DMA1_IRQHandler
PUBWEAK DMA2_IRQHandler
PUBWEAK DMA3_IRQHandler
PUBWEAK FTFA_IRQHandler
PUBWEAK PMU_IRQHandler
PUBWEAK LLWU_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK SPI0_IRQHandler
PUBWEAK SPI1_IRQHandler
PUBWEAK UART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK UART2_IRQHandler
PUBWEAK ADC0_IRQHandler
PUBWEAK CMP0_IRQHandler
PUBWEAK TPM0_IRQHandler
PUBWEAK TPM1_IRQHandler
PUBWEAK TPM2_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK PIT_IRQHandler
PUBWEAK USB_OTG_IRQHandler
PUBWEAK DAC0_IRQHandler
PUBWEAK TSI0_IRQHandler
PUBWEAK MCG_IRQHandler
PUBWEAK LPTMR0_IRQHandler
PUBWEAK PORTA_IRQHandler
PUBWEAK PORTD_IRQHandler
SECTION .text:CODE:REORDER(1)
THUMB
NMI_Handler
HardFault_Handler
SVC_Handler
PendSV_Handler
SysTick_Handler
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
FTFA_IRQHandler
PMU_IRQHandler
LLWU_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
TPM0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
RTC_Alarm_IRQHandler
RTC_IRQHandler
PIT_IRQHandler
USB_OTG_IRQHandler
DAC0_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTMR0_IRQHandler
PORTA_IRQHandler
PORTD_IRQHandler
Default_Handler
B Default_Handler
END
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:ROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD __iar_program_start ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete intertrupt
DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete intertrupt
DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete intertrupt
DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete intertrupt
DCD 0 ; 4: Reserved DMA Channel 5 transfer complete intertrupt
DCD FTFA_IRQHandler ; 5: FTFA
DCD PMU_IRQHandler ; 6: Low-voltage detect, low-voltage warning
DCD LLWU_IRQHandler ; 7: Low Leakage Wakeup
DCD I2C0_IRQHandler ; 8: IIC 0 interrupt
DCD I2C1_IRQHandler ; 9: IIC 1 intertrupt
DCD SPI0_IRQHandler ;10: SPI0 intertrupt
DCD SPI1_IRQHandler ;11: SPI1 intertrupt
DCD UART0_IRQHandler ;12: UART 0 status and error intertrupt
DCD UART1_IRQHandler ;13: UART 1 status and error intertrupt
DCD UART2_IRQHandler ;14: UART 2 status and error intertrupt
DCD ADC0_IRQHandler ;15: ADC 0 interrupt
DCD CMP0_IRQHandler ;16: CMP 0 interrupt
DCD TPM0_IRQHandler ;17: TPM 0 interrupt
DCD TPM1_IRQHandler ;18: TPM 1 interrupt
DCD TPM2_IRQHandler ;19: TPM 2 interrupt
DCD RTC_Alarm_IRQHandler ;20: RTC Alarm interrupt
DCD RTC_IRQHandler ;21: RTC Seconds interrupt
DCD PIT_IRQHandler ;22: PIT Single interrupt vector for all channels
DCD 0 ;23: Reserved
DCD USB_OTG_IRQHandler ;24: USB OTG intertrupt
DCD DAC0_IRQHandler ;25: UART 0 status intertrupt
DCD TSI0_IRQHandler ;26: TSI 0 interrupt
DCD MCG_IRQHandler ;27: MCG intertrupt
DCD LPTMR0_IRQHandler ;28: LPTMR0 intertrupt
DCD 0 ;29: Reserved
DCD PORTA_IRQHandler ;30: PORT A interrupt
DCD PORTD_IRQHandler ;31: PORT D interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
PUBWEAK NMI_Handler
PUBWEAK HardFault_Handler
PUBWEAK SVC_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK DMA0_IRQHandler
PUBWEAK DMA1_IRQHandler
PUBWEAK DMA2_IRQHandler
PUBWEAK DMA3_IRQHandler
PUBWEAK FTFA_IRQHandler
PUBWEAK PMU_IRQHandler
PUBWEAK LLWU_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK SPI0_IRQHandler
PUBWEAK SPI1_IRQHandler
PUBWEAK UART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK UART2_IRQHandler
PUBWEAK ADC0_IRQHandler
PUBWEAK CMP0_IRQHandler
PUBWEAK TPM0_IRQHandler
PUBWEAK TPM1_IRQHandler
PUBWEAK TPM2_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK PIT_IRQHandler
PUBWEAK USB_OTG_IRQHandler
PUBWEAK DAC0_IRQHandler
PUBWEAK TSI0_IRQHandler
PUBWEAK MCG_IRQHandler
PUBWEAK LPTMR0_IRQHandler
PUBWEAK PORTA_IRQHandler
PUBWEAK PORTD_IRQHandler
SECTION .text:CODE:REORDER(1)
THUMB
NMI_Handler
HardFault_Handler
SVC_Handler
PendSV_Handler
SysTick_Handler
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
FTFA_IRQHandler
PMU_IRQHandler
LLWU_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
TPM0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
RTC_Alarm_IRQHandler
RTC_IRQHandler
PIT_IRQHandler
USB_OTG_IRQHandler
DAC0_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTMR0_IRQHandler
PORTA_IRQHandler
PORTD_IRQHandler
Default_Handler
B Default_Handler
END
CODE
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000100;
define symbol __ICFEDIT_region_ROM_end__ = 0x0001ffff;
define symbol __ICFEDIT_region_RAM_start__ = 0x1ffff000;
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define symbol __region_RAM2_start__ = 0x20000000;
define symbol __region_RAM2_end__ = 0x20002fff;
define symbol __FlashConfig_start__ = 0x00000400;
define symbol __FlashConfig_end__ = 0x0000040f;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in FlashConfig_region {section FlashConfig};
place in ROM_region { readonly };
place in RAM_region { readwrite, block CSTACK, block HEAP };
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000100;
define symbol __ICFEDIT_region_ROM_end__ = 0x0001ffff;
define symbol __ICFEDIT_region_RAM_start__ = 0x1ffff000;
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define symbol __region_RAM2_start__ = 0x20000000;
define symbol __region_RAM2_end__ = 0x20002fff;
define symbol __FlashConfig_start__ = 0x00000400;
define symbol __FlashConfig_end__ = 0x0000040f;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in FlashConfig_region {section FlashConfig};
place in ROM_region { readonly };
place in RAM_region { readwrite, block CSTACK, block HEAP };
CODE
void NVIC_IntEnable(unsigned int IntNumber)
{
if(IntNumber>31) return;
NVIC_ISER |= (1UL<<IntNumber);
}
void NVIC_IntDisable(unsigned int IntNumber)
{
if(IntNumber>31) return;
NVIC_ICER |= (1UL<<IntNumber);
}
void NVIC_ClrPend(unsigned int IntNumber)
{
if(IntNumber>31) return;
NVIC_ICPR |= (1UL<<IntNumber);
}
void NVIC_IntPri(unsigned int IntNumber, unsigned char Priority)
{
if(IntNumber>31) return;
volatile unsigned char * pNVIC_IntPri = (unsigned char *)&NVIC_IPR0;
pNVIC_IntPri += IntNumber;
*pNVIC_IntPri = Priority;
}
void install_irq( unsigned int IntNumber, unsigned int Priority )
{
NVIC_IntDisable(IntNumber);
//NVIC_IntPri(IntNumber, Priority);
NVIC_IntEnable(IntNumber);
NVIC_ClrPend(IntNumber);
}
{
if(IntNumber>31) return;
NVIC_ISER |= (1UL<<IntNumber);
}
void NVIC_IntDisable(unsigned int IntNumber)
{
if(IntNumber>31) return;
NVIC_ICER |= (1UL<<IntNumber);
}
void NVIC_ClrPend(unsigned int IntNumber)
{
if(IntNumber>31) return;
NVIC_ICPR |= (1UL<<IntNumber);
}
void NVIC_IntPri(unsigned int IntNumber, unsigned char Priority)
{
if(IntNumber>31) return;
volatile unsigned char * pNVIC_IntPri = (unsigned char *)&NVIC_IPR0;
pNVIC_IntPri += IntNumber;
*pNVIC_IntPri = Priority;
}
void install_irq( unsigned int IntNumber, unsigned int Priority )
{
NVIC_IntDisable(IntNumber);
//NVIC_IntPri(IntNumber, Priority);
NVIC_IntEnable(IntNumber);
NVIC_ClrPend(IntNumber);
}
CODE
/*
* ISR for PIT interrupts
*/
//void pit_isr(void)
void PIT_IRQHandler(void)
{
volatile unsigned int dummy = PIT_TFLG0;
static int i=0;
if(dummy&PIT_TFLG_TIF_MASK)
{
PIT_TFLG0 = PIT_TFLG_TIF_MASK;
if(i)
{
i=0;
GPIOD_PCOR = 1ul<<18; //turn-on leds
}
else
{
i=1;
GPIOD_PSOR = 1ul<<18; //turn-off leds
}
}
}
//-----------------------------------
void PITInit(unsigned int period)
{
SIM_SCGC6 |= SIM_SCGC6_PIT_MASK; //разрешение тактирования
PIT_MCR = 0; //enable timers
// Timer 0
PIT_LDVAL0 = 4800000; //(SYS_CLK/period)-1; // setup ti
PIT_TCTRL0 = PIT_TCTRL_TIE_MASK; // enable Timer 1 interrupts
PIT_TCTRL0 |= PIT_TCTRL_TEN_MASK; // start Timer 1
// Timer 1
PIT_LDVAL1 = 4800000; //(SYS_CLK/period)-1; // setup ti
//PIT_TCTRL1 = PIT_TCTRL_TIE_MASK; // enable Timer 1 interrupts
PIT_TCTRL1 |= PIT_TCTRL_TEN_MASK; // start Timer 1
install_irq(PIT_irq_no, 0);
}
//-----------------------------------
* ISR for PIT interrupts
*/
//void pit_isr(void)
void PIT_IRQHandler(void)
{
volatile unsigned int dummy = PIT_TFLG0;
static int i=0;
if(dummy&PIT_TFLG_TIF_MASK)
{
PIT_TFLG0 = PIT_TFLG_TIF_MASK;
if(i)
{
i=0;
GPIOD_PCOR = 1ul<<18; //turn-on leds
}
else
{
i=1;
GPIOD_PSOR = 1ul<<18; //turn-off leds
}
}
}
//-----------------------------------
void PITInit(unsigned int period)
{
SIM_SCGC6 |= SIM_SCGC6_PIT_MASK; //разрешение тактирования
PIT_MCR = 0; //enable timers
// Timer 0
PIT_LDVAL0 = 4800000; //(SYS_CLK/period)-1; // setup ti
PIT_TCTRL0 = PIT_TCTRL_TIE_MASK; // enable Timer 1 interrupts
PIT_TCTRL0 |= PIT_TCTRL_TEN_MASK; // start Timer 1
// Timer 1
PIT_LDVAL1 = 4800000; //(SYS_CLK/period)-1; // setup ti
//PIT_TCTRL1 = PIT_TCTRL_TIE_MASK; // enable Timer 1 interrupts
PIT_TCTRL1 |= PIT_TCTRL_TEN_MASK; // start Timer 1
install_irq(PIT_irq_no, 0);
}
//-----------------------------------
Также дополнительно привожу нумерацию прерываний - эти индексы используются для разрешения/запрещения прерываний.
CODE
/* Interrupt Vector Table Function Pointers */
#define DMA0_irq_no 0 // Vector No 16
#define DMA1_irq_no 1 // Vector No 17
#define DMA2_irq_no 2 // Vector No 18
#define DMA3_irq_no 3 // Vector No 19
#define FTFA_irq_no 5 // Vector No 21
#define LVD_irq_no 6 // Vector No 22
#define LLWU_irq_no 7 // Vector No 23
#define I2C0_irq_no 8 // Vector No 24
#define I2C1_irq_no 9 // Vector No 25
#define SPI0_irq_no 10 // Vector No 26
#define SPI1_irq_no 11 // Vector No 27
#define UART0SE_irq_no 12 // Vector No 28
#define UART1SE_irq_no 13 // Vector No 29
#define UART2SE_irq_no 14 // Vector No 30
#define ADC0_irq_no 15 // Vector No 31
#define CMP0_irq_no 16 // Vector No 32
#define FTM0_irq_no 17 // Vector No 33
#define FTM1_irq_no 18 // Vector No 34
#define FTM2_irq_no 19 // Vector No 35
#define RTCA_irq_no 20 // Vector No 36
#define RTCS_irq_no 21 // Vector No 37
#define PIT_irq_no 22 // Vector No 38
#define USBOTG_irq_no 24 // Vector No 40
#define DAC_irq_no 25 // Vector No 41
#define TSI_irq_no 26 // Vector No 42
#define MCG_irq_no 27 // Vector No 43
#define LPTMR_irq_no 28 // Vector No 44
#define PortA_irq_no 30 // Vector No 46
#define PortD_irq_no 31 // Vector No 47
#define DMA0_irq_no 0 // Vector No 16
#define DMA1_irq_no 1 // Vector No 17
#define DMA2_irq_no 2 // Vector No 18
#define DMA3_irq_no 3 // Vector No 19
#define FTFA_irq_no 5 // Vector No 21
#define LVD_irq_no 6 // Vector No 22
#define LLWU_irq_no 7 // Vector No 23
#define I2C0_irq_no 8 // Vector No 24
#define I2C1_irq_no 9 // Vector No 25
#define SPI0_irq_no 10 // Vector No 26
#define SPI1_irq_no 11 // Vector No 27
#define UART0SE_irq_no 12 // Vector No 28
#define UART1SE_irq_no 13 // Vector No 29
#define UART2SE_irq_no 14 // Vector No 30
#define ADC0_irq_no 15 // Vector No 31
#define CMP0_irq_no 16 // Vector No 32
#define FTM0_irq_no 17 // Vector No 33
#define FTM1_irq_no 18 // Vector No 34
#define FTM2_irq_no 19 // Vector No 35
#define RTCA_irq_no 20 // Vector No 36
#define RTCS_irq_no 21 // Vector No 37
#define PIT_irq_no 22 // Vector No 38
#define USBOTG_irq_no 24 // Vector No 40
#define DAC_irq_no 25 // Vector No 41
#define TSI_irq_no 26 // Vector No 42
#define MCG_irq_no 27 // Vector No 43
#define LPTMR_irq_no 28 // Vector No 44
#define PortA_irq_no 30 // Vector No 46
#define PortD_irq_no 31 // Vector No 47