`timescale 1ns/1ns
module ADC_send (
input clk,
input reset,
input DOUT,
input [7:0] data_send, //flag data_send
output wire [11:0] DATA_w [7:0],
output wire SCLK_w,
output wire [7:0] nCS_w,
output wire [7:0] new_data,
output wire [7:0] GOOD_ADC_w/*ADDED*/,
output wire [1:0] state_w,
output wire [3:0] N_w
);
parameter DELAY=1;
reg [7:0] new_data_r; //flag new_data
reg [3:0] N; //bit pointer
reg [2:0] S; //adress
reg [1:0] state; //state-machine
reg [7:0] nCS; //CS_ADC
reg [11:0] DATA [7:0]; //data_out
reg SCLK_en; //enable CLK_ADC
reg [3:0] WDT; //Watchdog Timer (7.5 us ADC MAX1241) Tclk*
reg [7:0] GOOD_ADC; //ADC condition

parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
//ADDED
assign state_w = state;
assign N_w = N;
//


// Output depends only on the state
always @ (posedge clk or negedge reset) begin
if (!reset) begin
DATA[0][11:0] <= #DELAY 0; DATA[1][11:0] <= #DELAY 0; DATA[2][11:0] <= #DELAY 0; DATA[3][11:0] <= #DELAY 0;
DATA[4][11:0] <= #DELAY 0; DATA[5][11:0] <= #DELAY 0; DATA[6][11:0] <= #DELAY 0; DATA[7][11:0] <= #DELAY 0;
S <= #DELAY 3'd0;
N <= #DELAY 4'd0;
nCS <= #DELAY 8'hFF;
// new_data_r <= #DELAY 7'd0;
end
else begin
case (state)
S0: //start
begin
N <= #DELAY 4'd0;
nCS <= #DELAY 8'hFF; //>=220 ns for MAX1241
end
S1: //nCS
begin
//nCS [S] <= #DELAY 1'd0;
nCS [S] <= #DELAY 1'd0;
end
S3: //WR data
begin
N <= #DELAY N + 4'd1; //ukazatel' byte
if (WDT >= 4'h8) begin
S <= #DELAY S + 3'd1;
end
else if (N <= 12) begin
DATA [S][11-N] <= #DELAY DOUT;
end
else if (N == 13/*14*/) begin //end
new_data_r [S] <= #DELAY 1;
end
else if (N == 14/*15*/) begin //end
S <= #DELAY S + 3'd1;
end
end
endcase
end
if (!reset)
new_data_r[0] <= #DELAY 0;
else if (data_send[0])
new_data_r[0] <= #DELAY 0;
if (!reset)
new_data_r[1] <= #DELAY 0;
else if (data_send[1])
new_data_r[1] <= #DELAY 0;
if (!reset)
new_data_r[2] <= #DELAY 0;
else if (data_send[2])
new_data_r[2] <= #DELAY 0;
if (!reset)
new_data_r[3] <= #DELAY 0;
else if (data_send[3])
new_data_r[3] <= #DELAY 0;
if (!reset)
new_data_r[4] <= #DELAY 0;
else if (data_send[4])
new_data_r[4] <= #DELAY 0;
if (!reset)
new_data_r[5] <= #DELAY 0;
else if (data_send[5])
new_data_r[5] <= #DELAY 0;
if (!reset)
new_data_r[6] <= #DELAY 0;
else if (data_send[6])
new_data_r[6] <= #DELAY 0;
if (!reset)
new_data_r[7] <= #DELAY 0;
else if (data_send[7])
new_data_r[7] <= #DELAY 0;
end

// Determine the next state
always @ (posedge clk or negedge reset) begin
if (!reset) begin
state <= #DELAY S0;
SCLK_en <= #DELAY 1'd0;
GOOD_ADC <= #DELAY 8'hFF;
end
else
case (state)
S0: begin
state <= #DELAY S1;
SCLK_en <= #DELAY 1'd0;
end
S1: begin
state <= #DELAY S2;
SCLK_en <= #DELAY 1'd0;
WDT <= #DELAY 4'h0;
end
S2: begin
if (DOUT) begin //sCLK ADC, response waiting
state <= #DELAY S3; //next
SCLK_en <= #DELAY 1'd1;
GOOD_ADC[S] <= #DELAY 1'h1;
end
else if (WDT < 4'h8) begin //response waiting
state <= #DELAY S2;
SCLK_en <= #DELAY 1'd0;
WDT <= #DELAY WDT + 4'h1;
end
else if (WDT >= 4'h8) begin
state <= #DELAY S3;
GOOD_ADC[S] <= #DELAY 1'h0;
end
end
S3: begin
//else if (N != 15) //write data
//else if (N < 15) //write data
if (N < 14) //write data
state <= #DELAY S3;
//else if (N == 15)
//else if (N >= 15)
else if (N >= 14)
state <= #DELAY S0;
end
endcase
end

assign GOOD_ADC_w = GOOD_ADC;
assign SCLK_w = SCLK_en ? clk : 1'd0;
assign DATA_w = DATA;
assign nCS_w = nCS;
assign new_data = new_data_r;

endmodule

derive_clock_uncertainty
create_clock -period 8MHz -name {clk} [get_ports {clk}]
create_generated_clock -name {clk_div_8} -divide_by 8 -source [get_ports {clk}] [get_registers {cnt[2]}]

set_clock_groups -exclusive -group {clk}
set_clock_groups -exclusive -group {clk_div_8}