----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    16:38:07 12/27/2012
-- Design Name:
-- Module Name:    Generator_1_19 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Generator_1_19 is
    Port ( clk : in  STD_LOGIC;
           dann_out : out  STD_LOGIC);
end Generator_1_19;

architecture Behavioral of Generator_1_19 is
signal reg:std_logic:='0';
signal count:integer range 0 to 20:=0;
begin
dann_out<=reg;
p1:process(clk)
begin
if (clk'event and clk='1') then
    if (count=19) then
        reg<='1';
        count<=0;
    else
        reg<='0';
        count<=count+1;
    end if;
    
end if;
end process;

end Behavioral;

module top (
  input clk,    // 50 MHz clock input.
  input rst,

  output reg imp // Signal pulse.
  );
  
  parameter SYS_CLK_MHZ     = 50;  // System clock frequency, MHz.
  parameter PULSE_WIDTH_NS  = 200; // Pulse width, ns.
  parameter PULSE_PERIOD_US = 100; // Pulse period, us.
  
  localparam PULSE_WIDTH = (SYS_CLK_MHZ * PULSE_WIDTH_NS) / 1000; // Pulse width, clock cycles.
  localparam PULSE_PERIOD = (SYS_CLK_MHZ * PULSE_PERIOD_US); // Pulse period, clock cycles.
  
  localparam PULSE_PERIOD_W = $clog2(PULSE_PERIOD); // Pulse period counter width.
  
  reg [PULSE_PERIOD_W - 1 :0] period_cntr; // Pulse period counter.
  
  always_ff @(posedge clk, posedge rst)
  if (rst)
    begin
      period_cntr <= '0;
      imp <= '1;
    end
  else
    begin
      period_cntr <= period_cntr + 1;
      if (PULSE_PERIOD == period_cntr) period_cntr <= '0;
      if (PULSE_WIDTH == period_cntr)  imp <= '0;
      if (PULSE_PERIOD == period_cntr) imp <= '1;
    end

endmodule