In some cases, one or more I/O banks in an FPGA are not used (for example, when an FPGA has far more I/O pins than the design requires). In these cases, it might be desirable to leave the bank’s associated VCCO pins unconnected, as it can free up some PCB layout constraints (less voiding of power and ground planes from via antipads, less obstacles to signals entering and exiting the pinout array, more copper area available for other planelets in the otherwise used plane layer).
Leaving the VCCO pins of unused I/O banks floating reduces the level of ESD protection on these pins and the I/O pins in the bank. However, ESD events at the unconnected solder balls in the inner rows of the pinout array are unlikely and not considered a high risk.