in_f : fifo PORT MAP(clk64MHz_in , Ext_Din, '1', '1', sign16_input, open, open );
in_fir: input_fir port map(clk64MHz_in, open, open, sign16_input, sign16_iFifo_out);
in_g : input_gain PORT MAP(sign16_iFifo_out, sign16_iGain_out);
dds : geterodin PORT MAP(clk64MHz_in, sign10_cosine, sign10_sine);
mix_i : signmult PORT MAP(clk64MHz_in, sign10_sine, sign16_iGain_out, sign26_iMixer_i);
mix_r : signmult PORT MAP(clk64MHz_in, sign10_cosine,sign16_iGain_out, sign26_iMixer_r);
fir_i : flf port map(clk64MHz_in, open, open, sign26_iMixer_i , sign18_lFIR_i);
fir_r : flf port map(clk64MHz_in, open, open, sign26_iMixer_r , sign18_lFIR_r);
gain_i: amp_mix PORT MAP(sign18_lFIR_i, sign18_Gain_i);
gain_r: amp_mix PORT MAP(sign18_lFIR_r, sign18_Gain_r);
dec_r : fir_int port map(clk64MHz_in,open,open,sign18_dec03_to_FIR_r,sign18_dec04_r); --125k -> 15625
dec_i : fir_int port map(clk64MHz_in,open,open,sign18_dec03_to_FIR_i,sign18_dec04_i); --125k -> 15625
dec2_r: fir_int_2 port map(clk64MHz_in,open,open,sign18_dec02_to_FIR_r,sign18_dec03_r); --1M -> 125k
dec2_i: fir_int_2 port map(clk64MHz_in,open,open,sign18_dec02_to_FIR_i,sign18_dec03_i); --1M -> 125k
dec3_r: fir_int_3 port map(clk64MHz_in,open,open,sign18_dec01_to_FIR_r,sign18_dec02_r); --8M -> 1M
dec3_i: fir_int_3 port map(clk64MHz_in,open,open,sign18_dec01_to_FIR_i,sign18_dec02_i); --8M -> 1M
dec4_r: fir_int_4 port map(clk64MHz_in,open,open,sign18_Gain_r,sign18_dec01_r); --64M -> 8M
dec4_i: fir_int_4 port map(clk64MHz_in,open,open,sign18_Gain_i,sign18_dec01_i); --64M -> 8M
lf_r : lf port map(clk64MHz_in,open,open,sign18_fir_lf_r,sign18_mem_in);
lf_i : lf port map(clk64MHz_in,open,open,sign18_fir_lf_i,sign18_mem_in_i);
mem_R : memory PORT MAP(sign_clk_15625Hz,sign_mem_en,sign18_mem_addr,sign18_mem_in(17 downto 8),sign18_mem_out(17 downto 8));
mem_I : memory PORT MAP(sign_clk_15625Hz,sign_mem_en_i,sign18_mem_addr_i,sign18_mem_in_i(17 downto 8),sign18_mem_out_i(17 downto 8));
fnch_r: fir_int port map(clk64MHz_in,open,open,sign18_int03_to_FIR_r,sign18_int03_r);
fnch_i: fir_int port map(clk64MHz_in,open,open,sign18_int03_to_FIR_i,sign18_int03_i);
fnch2_r: fir_int_2 port map(clk64MHz_in,open,open,sign18_int02_to_FIR_r,sign18_int02_r);
fnch2_i: fir_int_2 port map(clk64MHz_in,open,open,sign18_int02_to_FIR_i,sign18_int02_i);
fnch3_r: fir_int_3 port map(clk64MHz_in,open,open,sign18_int01_to_FIR_r,sign18_int01_r);
fnch3_i: fir_int_3 port map(clk64MHz_in,open,open,sign18_int01_to_FIR_i,sign18_int01_i);
fnch4_r: fir_int_4 port map(clk64MHz_in,open,open,sign18_int00_to_FIR_r,sign18_r);
fnch4_i: fir_int_4 port map(clk64MHz_in,open,open,sign18_int00_to_FIR_i,sign18_i);
-------------------------------------------------------------------------------------------------------
data_out_pr : process (clk64MHz_in)
begin
if clk64MHz_in'event and clk64MHz_in ='1' then
sign18_out_data_in <= sign18_Gain_r;
if cas= '0' then
cas <= '1';
if sign_play = '1' then
sign18_out_data <= sign18_r;
else
sign18_out_data <= "000000000000000000";
end if;
else
cas <= '0';
if sign_play = '1' then
sign18_out_data <= sign18_i;
else
sign18_out_data <= "000000000000000000";
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------------
data_out_pr66 : process (clk64MHz_in)
begin
if sign_clk_15625Hz'event and sign_clk_15625Hz ='1' then
sign18_out_data_pow <= sign18_int02_r;
sign18_out_data_prd <= sign18_int02_i;
end if;
end process;
-------------------------------------------------------------------------------------------------------
decimation1 : process (sign_clk_8MHz)
begin
if sign_clk_8MHz'event and sign_clk_8MHz ='1' then
if clk64MHz_in'event and clk64MHz_in ='1' then
sign18_dec01_to_FIR_r <= sign18_dec01_r;
sign18_dec01_to_FIR_i <= sign18_dec01_i;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------
decimation2 : process (sign_clk_1MHz)
begin
if sign_clk_1MHz'event and sign_clk_1MHz ='1' then
if sign_clk_8MHz'event and sign_clk_8MHz ='1' then
sign18_dec02_to_FIR_r <= sign18_dec02_r;
sign18_dec02_to_FIR_i <= sign18_dec02_i;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------
decimation3 : process (sign_clk_125kHz)
begin
if sign_clk_125kHz'event and sign_clk_125kHz ='1' then
if sign_clk_1MHz'event and sign_clk_1MHz ='1' then
sign18_dec03_to_FIR_r <= sign18_dec03_r;
sign18_dec03_to_FIR_i <= sign18_dec03_i;
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------------
interpolation1 : process (sign_clk_125kHz)
variable i1 : integer := 1;
begin
if sign_clk_125kHz'event and sign_clk_125kHz ='1' then
if i1 = 1 then
sign18_int03_to_FIR_r <= sign18_mem_in;
sign18_int03_to_FIR_i <= sign18_mem_in_i;
i1 := i1 + 1;
elsif i1 = 8 then
sign18_int03_to_FIR_r <= "000000000000000000"; --sign18_mem_out;
sign18_int03_to_FIR_i <= "000000000000000000"; --sign18_mem_out_i;
i1 := 1;
else
sign18_int03_to_FIR_r <= "000000000000000000"; --sign18_mem_out;
sign18_int03_to_FIR_i <= "000000000000000000"; --sign18_mem_out_i;
i1 := i1 + 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------------
interpolation2 : process (sign_clk_1MHz)
variable i2 : integer := 1;
begin
if sign_clk_1MHz'event and sign_clk_1MHz ='1' then
if i2 = 1 then
sign18_int02_to_FIR_r <= sign18_int03_r;
sign18_int02_to_FIR_i <= sign18_int03_i;
i2:= i2 + 1;
elsif i2=8 then
sign18_int02_to_FIR_r <= "000000000000000000"; --sign18_int03_r;
sign18_int02_to_FIR_i <= "000000000000000000"; --sign18_int03_i;
i2:= 1;
else
sign18_int02_to_FIR_r <= "000000000000000000"; --sign18_int03_r;
sign18_int02_to_FIR_i <= "000000000000000000"; --sign18_int03_i;
i2 := i2 + 1;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------------
interpolation3 : process (sign_clk_8MHz)
variable i3 : integer := 1;
begin
if sign_clk_8MHz'event and sign_clk_8MHz ='1' then
if i3 = 1 then
sign18_int01_to_FIR_r <= sign18_int02_r;
sign18_int01_to_FIR_i <= sign18_int02_i;
i3:=i3 + 1;
elsif i3=8 then
sign18_int01_to_FIR_r <= "000000000000000000"; --sign18_int02_r;
sign18_int01_to_FIR_i <= "000000000000000000"; --sign18_int02_i;
i3:= 1;
else
sign18_int01_to_FIR_r <= "000000000000000000"; --sign18_int02_r;
sign18_int01_to_FIR_i <= "000000000000000000"; --sign18_int02_i;
i3 := i3 + 1;
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------------------
interpolation4 : process (clk64MHz_in)
variable i4 : integer := 1;
begin
if clk64MHz_in'event and clk64MHz_in ='1' then
if i4 = 1 then
sign18_int00_to_FIR_r <= sign18_int01_r;
sign18_int00_to_FIR_i <= sign18_int01_i;
i4:=i4 + 1;
elsif i4=8 then
sign18_int00_to_FIR_r <= "000000000000000000"; --sign18_int01_r;
sign18_int00_to_FIR_i <= "000000000000000000"; --sign18_int01_i;
i4:= 1;
else
sign18_int00_to_FIR_r <= "000000000000000000"; --sign18_int01_r;
sign18_int00_to_FIR_i <= "000000000000000000"; --sign18_int01_i;
i4 := i4 + 1;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------
-- interpolation1 : process (sign_clk250_out)
-- begin
-- if sign_clk250_out'event and sign_clk250_out ='1' then
-- if sign_play = '1' then
-- if sign = 0 then
-- temp <= sign18_mem_out;
-- temp_i <= sign18_mem_out_i;
-- k <= sign18_mem_out - temp;
-- k1 <= sign18_mem_out_i - temp_i;
-- sign18_r <= temp;
-- sign18_i <= temp_i;
-- sign <= sign + 1;
-- elsif sign > 0 and sign/=255 then
-- sign18_r <= sign18_r + (k(17)&k(17)&k(17)&k(17)&k(17)&k(17)&k(17)&k(17)&k(17)&k(16 downto 8)) ;
-- sign18_i <= sign18_i + (k1(17)&k1(17)&k1(17)&k1(17)&k1(17)&k1(17)&k1(17)&k1(17)&k1(17)&k1(16 downto 8)) ;
-- sign <= sign + 1;
-- elsif sign = 255 then
-- sign18_r <= sign18_r + (k(17)&k(17)&k(17)&k(17)&k(17)&k(17)&k(17)&k(17)&k(17)&k(16 downto 8)) ;
-- sign18_i <= sign18_i + (k1(17)&k1(17)&k1(17)&k1(17)&k1(17)&k1(17)&k1(17)&k1(17)&k1(17)&k1(16 downto 8)) ;
-- sign <= 0;
-- end if;
-- elsif sign_play = '0' then
-- temp <= "000000000000000000";
-- temp_i <= "000000000000000000";
-- end if;
-- end if;
-- end process;
---------------------------------------------------------------------------------------------------------
dec_64MHz_to_8MHz : process (clk64MHz_in)
begin
if clk64MHz_in'event and clk64MHz_in ='1' then
case dCount2 is
when 4 =>
dCount1 <= 1;
sign_clk_8MHz <= not sign_clk_8MHz ;
when others =>
dCount1 <= dCount1 + 1;
end case;
end if;
end process;
--------------------------------------------------------------------------------------------------------
dec_64MHz_to_1MHz : process (clk64MHz_in)
begin
if clk64MHz_in'event and clk64MHz_in ='1' then
case dCount2 is
when 32 =>
dCount2 <= 1;
sign_clk_1MHz <= not sign_clk_1MHz;
when others =>
dCount2 <= dCount2 + 1;
end case;
end if;
end process;
--------------------------------------------------------------------------------------------------------
dec_64MHz_to_125kHz : process (clk64MHz_in)
begin
if clk64MHz_in'event and clk64MHz_in ='1' then
case dCount3 is
when 256 =>
dCount3 <= 1;
sign_clk_125kHz <= not sign_clk_125kHz;
when others =>
dCount3 <= dCount3 + 1;
end case;
end if;
end process;
-------------------------------------------------------------------------------------------------------
dec_64MHz_to_16kHz : process (clk64MHz_in)
begin
if clk64MHz_in'event and clk64MHz_in ='1' then
case dCount4 is
when 1>
dCount4 <= dCount4 + 1;
sign_clk_15625Hz <= '1';
sign18_fir_lf_r <= sign18_Gain_r;
sign18_fir_lf_i <= sign18_Gain_i;
when 2001 =>
dCount4 <= dCount4 + 1;
sign_clk_15625Hz <= '0';
when 4000 =>
dCount4 <= 1;
when others =>
dCount4 <= dCount4 + 1;
end case;
end if;
end process;
-------------------------------------------------------------------------------------------------------
data_out_memory : process (sign_clk_15625Hz)
begin
if sign_clk_15625Hz'event and sign_clk_15625Hz ='0' then
case count_w is
when 0 to 159999 => -- запись
sign_mem_en <= "1"; -- строб записи
sign_mem_en_i<= "1"; -- строб записи
adrr_e <= adrr_e + "000000000000000001"; -- переход к следующей ячейке памяти
sign18_mem_addr <= adrr_e; -- выставление адреса на блоке памяти
sign18_mem_addr_i<= adrr_e; -- выставление адреса на блоке памяти
count_w <= count_w + 1; -- инкремент счетчика
sign_play <= '0';
when 160000 => -- ожидание
sign_mem_en <= "0"; -- строб записи
sign_mem_en_i <= "0"; -- строб записи
count_w <= count_w + 1; --
adrr_e <= "000000000000000000"; -- переход к 0 адресу
sign_play <= '0';
when 320000 to 479999 => -- воспроизведение
sign_play <= '1';
sign_mem_en <= "0";
sign_mem_en_i<= "0";
adrr_e <= adrr_e + "000000000000000001";
sign18_mem_addr <= adrr_e;
sign18_mem_addr_i <= adrr_e;
count_w <= count_w + 1;
when 480000 =>
count_w <= 0;
adrr_e <= "000000000000000000";
sign_play <= '0';
when others =>
count_w <= count_w + 1;
sign_play <= '0';
end case;
end if;
end process;