void OW_Init(){
    GPIO_InitTypeDef GPIO_InitStructure;
    USART_InitTypeDef USART_InitStructure;
    
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
      RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);

    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_10;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
    GPIO_Init(GPIOA, &GPIO_InitStructure); //TX
    
    GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1);
    GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1);
    
    USART_InitStructure.USART_BaudRate = 115200;
    USART_InitStructure.USART_WordLength = USART_WordLength_8b;
    USART_InitStructure.USART_StopBits = USART_StopBits_1;
    USART_InitStructure.USART_Parity = USART_Parity_No;
    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
    USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
    USART_Init(USART_X, &USART_InitStructure);
    USART_Cmd(USART_X, ENABLE);
    
    DMA_DeInit(DMA_TX_STREAM);
    DMA_InitStructureTX.DMA_Channel = DMA_CHANNEL;
    DMA_InitStructureTX.DMA_DIR = DMA_DIR_MemoryToPeripheral; // Transmit
    DMA_InitStructureTX.DMA_Memory0BaseAddr = (uint32_t) ow_buf;
    DMA_InitStructureTX.DMA_PeripheralBaseAddr = (uint32_t) &(USART_X->DR);
    DMA_InitStructureTX.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
    DMA_InitStructureTX.DMA_MemoryInc = DMA_MemoryInc_Enable;
    DMA_InitStructureTX.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
    DMA_InitStructureTX.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
    DMA_InitStructureTX.DMA_Mode = DMA_Mode_Normal;
    DMA_InitStructureTX.DMA_Priority = DMA_Priority_High;
    DMA_InitStructureTX.DMA_FIFOMode = DMA_FIFOMode_Enable;
    DMA_InitStructureTX.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
    DMA_InitStructureTX.DMA_MemoryBurst = DMA_MemoryBurst_Single;
    DMA_InitStructureTX.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
    
    DMA_DeInit(DMA_RX_STREAM);
    DMA_InitStructureRX.DMA_Channel = DMA_CHANNEL;
    DMA_InitStructureRX.DMA_DIR = DMA_DIR_PeripheralToMemory; // Receive
    DMA_InitStructureRX.DMA_Memory0BaseAddr = (uint32_t) ow_buf;
    DMA_InitStructureRX.DMA_PeripheralBaseAddr = (uint32_t) &(USART_X->DR);
    DMA_InitStructureRX.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
    DMA_InitStructureRX.DMA_MemoryInc = DMA_MemoryInc_Enable;
    DMA_InitStructureRX.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
    DMA_InitStructureRX.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
    DMA_InitStructureRX.DMA_Mode = DMA_Mode_Normal;
    DMA_InitStructureRX.DMA_Priority = DMA_Priority_High;
    DMA_InitStructureRX.DMA_FIFOMode = DMA_FIFOMode_Enable;
    DMA_InitStructureRX.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
    DMA_InitStructureRX.DMA_MemoryBurst = DMA_MemoryBurst_Single;
    DMA_InitStructureRX.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
    
}

void OW_SendBits(uint8_t nbits){
    
    DMA_DeInit(DMA_TX_STREAM);
    DMA_DeInit(DMA_RX_STREAM);
    DMA_InitStructureTX.DMA_BufferSize = nbits;
    DMA_InitStructureRX.DMA_BufferSize = nbits;
    DMA_Init(DMA_TX_STREAM, &DMA_InitStructureTX);
    DMA_Init(DMA_RX_STREAM, &DMA_InitStructureRX);
  
    USART_ClearFlag(USART_X, USART_FLAG_RXNE | USART_FLAG_TC | USART_FLAG_TXE);
    USART_DMACmd(USART_X, USART_DMAReq_Tx | USART_DMAReq_Rx, ENABLE);
    
    DMA_Cmd(DMA_RX_STREAM, ENABLE);
    DMA_Cmd(DMA_TX_STREAM, ENABLE);

    while(DMA_GetFlagStatus(DMA_TX_STREAM, DMA_FLAG_TCIF7) == RESET);

    DMA_Cmd(DMA_TX_STREAM, DISABLE);
    DMA_Cmd(DMA_RX_STREAM, DISABLE);
    
    USART_DMACmd(USART_X, USART_DMAReq_Tx | USART_DMAReq_Rx, DISABLE);
}

#define USART_X                        USART1
#define DMA_TX_STREAM           DMA2_Stream7
#define DMA_RX_STREAM           DMA2_Stream2
#define DMA_CHANNEL                DMA_Channel_4