void (*Entry_Point)(void);
Entry_Point = (void(*)(void))(USER_CODE);
Entry_Point();

ResetStart
    LDR     PC, ResetAddr
    LDR     PC, UndefinedAddr
    LDR     PC, SWI_Addr
    LDR     PC, PrefetchAddr
    LDR     PC, DataAbortAddr
    LDR     PC, ReservedAddr
    LDR     PC, IRQ_Addr
    LDR     PC, FIQ_Addr

InitStack    
    MOV     R0, LR
;Build the SVC stack
    MSR     CPSR_c, #SVC32Mode :OR: I_BIT :OR: F_BIT        
    LDR     SP, StackSvc    
;Build the IRQ stack
    MSR     CPSR_c, #IRQ32Mode :OR: I_BIT :OR: F_BIT
    LDR     SP, StackIrq
;Build the FIQ stack
    MSR     CPSR_c, #FIQ32Mode :OR: I_BIT :OR: F_BIT
    LDR     SP, StackFiq
;Build the DATAABORT stack
    MSR     CPSR_c, #ABT32Mode :OR: I_BIT :OR: F_BIT
    LDR     SP, StackAbt
;Build the UDF stack
    MSR     CPSR_c, #UDF32Mode :OR: I_BIT :OR: F_BIT
    LDR     SP, StackUnd
;Build the SYS stack
    MSR     CPSR_c, #SYS32Mode :OR: I_BIT :OR: F_BIT
    LDR     SP, =StackUsr
    MSR     CPSR_c, #SYS32Mode
    BX      R0

    PRESERVE8

VECTOR_RAM_SRC    EQU        0x80000000
VECTOR_FLASH_SRC    EQU        0x20000000
VECTOR_DST        EQU        0x00000000

    EXPORT VectorRemap
    AREA BlockCopy, CODE, READONLY     ; name this block of code

VectorRemap
    STMFD   sp!, {r0, r1, r4-r11}; save registers
    IF :DEF: REMAP_RAM
    LDR     r0, =VECTOR_RAM_SRC
    ELSE
    LDR     r0, =VECTOR_FLASH_SRC; r0 = pointer to source block
    ENDIF
    LDR     r1, =VECTOR_DST        ; r1 = pointer to destination block      
    LDMIA   r0!, {r4-r11}        ; remap first 16 words from 0x20000000
    STMIA   r1!, {r4-r11}        ; to address 0x00000000 for interrupt
    LDMIA   r0!, {r4-r11}        ; exception handler
    STMIA   r1!, {r4-r11}  
    LDMFD   sp!, {r0, r1, r4-r11}; restore registers

    END

        AREA    MyVectors, DATA, NOINIT, ALIGN=4

LR_IROM1 0x20000000 0x00080000  {   ; load region size_region
  ER_IROM1 0x20000000 0x00080000  { ; load address = execution address
   *.o (RESET, +First)
   *(InRoot$$Sections)
   .ANY (+RO)
  }
  RW_IRAM1 0x80000000 0x0000E000  { ; RW data
   *.o (RAMFUNC)
   .ANY (+RW +ZI)
  }
  RW_IRAM2 0x00000000 0x00008000 {; 16 KB TCM memory
   *.o (MyVectors)
  }
}

MRC p15, 0, <Rd>, c1, c0, 0
MCR p15, 0, <Rd>, c1, c0, 0

LR_IROM1 0x20000000 0x00080000  {; load region size_region
  ER_IROM1 0x20000000 0x00080000  {; load address = execution address
   *.o (RESET, +First)
   *(InRoot$$Sections)
   .ANY (+RO)
  }
  RW_IRAM1 0x80000000 0x0000E000  {; RW data
   *.o (RAMFUNC)
   .ANY (+RW +ZI)
  }
  RW_IRAM2 0x00000000 0x00008000 {; 16 KB TCM memory
   *.o (MyVectors)
  }
}

    MRC     p15, 0, r4, c1, c0, 0; Read CP15
    ORR     r4, r4, #DTCM_enabled; Enable Data TCM
; At power up, the interrupt vector is mapped to addr. 0 already,
; enabling instruction TCM will wipe out the mirror of the
; vector table. A remap will be performed there after. */
    ORR     r4, r4, #ITCM_enabled; Enable Instruction TCM
    ORR     r4, r4, #WB_enabled; Enable Write Buffer
    MCR     p15, 0, r4, c1, c0, 0; Write CP15

LR_IROM1 0x20000000 0x00080000  {; load region size_region
  ER_IROM1 0x20000000 0x00080000  {; load address = execution address
   *.o (RESET, +First)
   *(InRoot$$Sections)
   .ANY (+RO)
  }
  RW_IRAM1 0x80000000 0x0000E000  {; RW data
   *.o (RAMFUNC)
   .ANY (+RW +ZI)
  }
  RW_IRAM2 0xFFFF0000 0xFFFF001C {; Vectors in HI
   *.o (MyVectors)
  }
}

VBIT_enabled    EQU    1<<13


    MRC     p15, 0, r4, c1, c0, 0; Read CP15
    ORR     r4, r4, #VBIT_enabled; Enable Vector location bit to 0xFFFF0000
    MCR     p15, 0, r4, c1, c0, 0; Write CP15