Сделал компонент для NIOS с выходом типа ARRAY. SOPS Builder во время анализа VHDL-кода говорит, что данный тип не поддерживается:
Error: Verilog HDL or VHDL XML Interface error at nios_comp_config_regs.vhd(31): port "out_regs" has an unsupported type...
Он и в самом деле не понимает тип ARRAY или я что-то не так делаю?
Вот кусок кода:
CODE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
package my_bus is
type BUS_ARRAY is array (15 downto 0) of STD_LOGIC_VECTOR (15 DOWNTO 0);
end my_bus;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_bus.all;
ENTITY config_regs16 IS
PORT
(
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
avalon_slave_address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
avalon_slave_byteenable: IN STD_LOGIC_VECTOR (3 DOWNTO 0) ;
avalon_slave_chipselect : IN STD_LOGIC;
avalon_slave_write : IN STD_LOGIC;
avalon_slave_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
avalon_slave_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
avalon_slave_read : IN STD_LOGIC;
out_regs : OUT BUS_ARRAY // строка 31!!!
);
END config_regs16;
ARCHITECTURE behavior OF config_regs16 IS
signal cfg_regs: BUS_ARRAY;
BEGIN
... тут тело
END behavior;
USE ieee.std_logic_1164.all;
LIBRARY work;
package my_bus is
type BUS_ARRAY is array (15 downto 0) of STD_LOGIC_VECTOR (15 DOWNTO 0);
end my_bus;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_bus.all;
ENTITY config_regs16 IS
PORT
(
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
avalon_slave_address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
avalon_slave_byteenable: IN STD_LOGIC_VECTOR (3 DOWNTO 0) ;
avalon_slave_chipselect : IN STD_LOGIC;
avalon_slave_write : IN STD_LOGIC;
avalon_slave_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
avalon_slave_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
avalon_slave_read : IN STD_LOGIC;
out_regs : OUT BUS_ARRAY // строка 31!!!
);
END config_regs16;
ARCHITECTURE behavior OF config_regs16 IS
signal cfg_regs: BUS_ARRAY;
BEGIN
... тут тело
END behavior;