ADC2->CR2 =
    ADC_CR2_ADON        * 1 |    // A/D Converter ON / OFF
    ADC_CR2_CONT        * 0 |    // Continuous Conversion
    ADC_CR2_DMA        * 0 |    // Direct Memory access mode
    ADC_CR2_DDS        * 0 |    // DMA disable selection (Single ADC)
    ADC_CR2_EOCS        * 0 |    // End of conversion selection
    ADC_CR2_ALIGN        * 0 |    // Data Alignment = Right
    ADC_CR2_JEXTSEL_0    * 1 |    // External event select for injected group - Bit 0 = EXTI_15 PG15
    ADC_CR2_JEXTSEL_1    * 1 |    //    Bit 1
    ADC_CR2_JEXTSEL_2    * 1 |    //    Bit 2
    ADC_CR2_JEXTSEL_3    * 1 |    //    Bit 3
    ADC_CR2_JEXTEN_0    * 0 |    // External Trigger Conversion mode for injected channels - Bit 0 = Fall
    ADC_CR2_JEXTEN_1    * 1 |    //    Bit 1
   ...

#define    ADC_CR2_JEXTSEL0    (ADC_CR2_JEXTSEL_0 * 0)
#define    ADC_CR2_JEXTSEL1    (ADC_CR2_JEXTSEL_0 * 1)
#define    ADC_CR2_JEXTSEL2    (ADC_CR2_JEXTSEL_0 * 2)
#define    ADC_CR2_JEXTSEL3    (ADC_CR2_JEXTSEL_0 * 3)
...
#define    ADC_CR2_JEXTSEL15  (ADC_CR2_JEXTSEL_0 * 15)

...
#define COMP(v,offset) ((v)<<offset)) //упрощенная версия
//используемые макросы (МК другой):
//#define ERROR_VALUE (_nop_())
//#define COMP(v,min,max,offset,len)  ((((v)<min)||((v)>max)||((v)>=1<<len)||((len+offset)>16)) ? ERROR_VALUE : ((v)<<offset))
...
#define ADON(v)    (v, 0)
#define CONT(v)    COMP(v, 1)
#define DMA(v)    COMP(v, 8)
#define DDS(v)    COMP(v, 9)
#define EOCS(v)    COMP(v,10)
#define _RIGHT    (0)
#define _LEFT    (1)
#define ALIGN(v)    COMP(v,11)
#define _TMR1_CC4 (0)
#define _EXTI_15    (15)
#define JEXTSEL(v)    COMP(v,16)
#define _RISING    (1)
#define _FALLING    (2)
#define JEXTEN(v)    COMP(v,20)
...
ADC_CR2=ADON(1) | CONT(1) | DMA(0) | DDS(0) | EOCS(0) | ALIGN (_RIGHT) | JEXTSEL (_EXTI_15) | JEXTEN(_FALLING);

  ADC2->JSQR =
    ADC_JSQR_JSQ4_0        * 15 |    // 4th conversion in injected sequence (0..18) - IN15
    ADC_JSQR_JL_0        * 00;    // Injected Sequence length (0..3) - 1 Conversion

  ADC2->CCR =
    ADC_CCR_MULTI_0        * 00 |    // MULTI[4:0] (Multi-ADC mode selection)
    ADC_CCR_DELAY_0        * 00 |    // DELAY[3:0] bits (Delay between 2 sampling phases)
    ADC_CCR_DDS        *  0 |    // DMA disable selection (Multi-ADC mode)
    ADC_CCR_DMA_0        * 00 |    // DMA[1:0] bits (Direct Memory Access mode for multimode)
    ADC_CCR_ADCPRE_0    * 00 |    // ADCPRE[1:0] bits (ADC prescaler) - PCLK2/2 = 30 MHz
    ADC_CCR_VBATE        *  1 |    // VBAT Enable
    ADC_CCR_TSVREFE        *  1;    // Temperature Sensor and VREFINT Enable