объясните как соблюсти требование к 4 клокам PCI для PC104+ 2.5 дюйма
если на плате стоит Mux/Demux

В спецификации же всё написано:
1) "The multiplexer chips are Dual 4:1 Mux/Demux chips. They provide a 5W switch that connects
the input and output together. These switches provide a bi-directional path with no signal
propagation delay other than the RC delay of the on resistance of the switch and the load
capacitance. This is typically 250ps at 50pF load."
2) "The clocks are tuned on the Host Board such that the length of CLK3 trace is »0.662" less than
CLK2, CLK2 trace is »0.662" less than CLK1, and CLK1 trace is »0.662" less than CLK0.
Therefore, the first module on the stack must select CLK0 (the longest trace), the second CLK1,
etc. This provides almost no clock skew between modules. Trace length limits are as indicated
in the PCI Local Bus Specification Revision 2.2."