Сделал вот так:
ARCHITECTURE beh OF Devider IS
signal cout: std_logic;
signal pos_cnt :std_logic_vector (1 downto 0);
signal neg_cnt :std_logic_vector (1 downto 0);
begin
process (takt, clr) begin
if (clr = '1') then
pos_cnt <= (others=>'0');
elsif (rising_edge(takt)) then
if conv_integer(pos_cnt)=2 then
pos_cnt<=conv_std_logic_vector (0,2);
else pos_cnt <= pos_cnt + 1;
end if;
end if;
end process;
process (takt, clr) begin
if (clr = '1') then
neg_cnt <= (others=>'0');
elsif (falling_edge(takt)) then
if conv_integer(neg_cnt)=2 then
neg_cnt<=conv_std_logic_vector (0,2);
else neg_cnt <= neg_cnt + 1;
end if;
end if;
end process;
cout <= '1' when ((pos_cnt /= 2) and (neg_cnt /= 2)) else
'0';
end architecture;
-не работает;(
Может посоветуете еще способы?
