while ( ( (SPI2 -> SR) & 0x2 ) == RESET)
    {
     //wait until TXE bit is 1
    }
    SPI2 -> DR = d0;

//=============================================================================
// SPI2 Related configuration
//=============================================================================
// enable SPI2 clock
((RCC_TypeDef *) (RCC_BASE))->APB1ENR |= RCC_APB1ENR_SPI2EN;


// configure SPI2
((SPI_TypeDef *) (SPI2_BASE)) -> CR1 |= (SPI_CR1_SPE | SPI_CR1_CPOL |
SPI_CR1_CPHA | SPI_CR1_MSTR |
SPI_CR1_BR_1 | SPI_CR1_SSM | SPI_CR1_SSI);

    while ( ( (SPI2 -> SR) & 0x2 ) == RESET)
    {
     //wait until TXE bit is 1
    }
    SPI2 -> DR = d0;

/* передача байта/слова, возврат считанного */
uint_fast16_t hardware_spi_word(
    uint_fast16_t v        /* значение байта для передачи */
    )
{
    (void) SPI1->DR;    /* clear SPI_SR_RXNE in status register */
    SPI1->DR = (v & SPI_DR_DR);

    // дождаться, пока последний байт выйдет из передатчика
    while ((SPI1->SR & SPI_SR_TXE) == 0)
    ;
    while(!(SPI1->SR & SPI_SR_RXNE))    /* Receive buffer Not Empty */
    ;

    return (SPI1->DR & SPI_DR_DR);
    
}

(void) SPI2->DR;    /* clear SPI_SR_RXNE in status register */
// breakpoint here!
SPI2->DR = (d0 & SPI_DR_DR);

while ((SPI2->SR & SPI_SR_TXE) == 0)
;

(void) SPI2->DR;    /* clear SPI_SR_RXNE in status register */
// breakpoint here!
SPI2->DR = (d0 & SPI_DR_DR);

while ((SPI2->SR & SPI_SR_TXE) == 0)
;

while ( (SPI2->SR & SPI_SR_TXE) ==0 );
sr_t = SPI2->SR;
cr1_t = SPI2->CR1;
cr2_t = SPI2->CR2;
// breakpoint here!
SPI2->DR = 0xAA;

while ( (SPI2->SR & SPI_SR_TXE) ==0 )
    {
    while(!(USART3->SR & USART_SR_TXE)); // check if TXE bit is set
    USART3->DR = (uint8_t)( (SPI2->SR)>>8 ); // sending a byte
    while(!(USART3->SR & USART_SR_TC)); // check if TC bit is set

    while(!(USART3->SR & USART_SR_TXE)); // check if TXE bit is set
    USART3->DR = (uint8_t)( SPI2->SR); // sending a byte
    while(!(USART3->SR & USART_SR_TC)); // check if TC bit is set
    }


while(!(USART3->SR & USART_SR_TXE)); // check if TXE bit is set
USART3->DR = (uint8_t)( (SPI2->SR)>>8 ); // sending a byte
while(!(USART3->SR & USART_SR_TC)); // check if TC bit is set

while(!(USART3->SR & USART_SR_TXE)); // check if TXE bit is set
USART3->DR = (uint8_t)( SPI2->SR); // sending a byte
while(!(USART3->SR & USART_SR_TC)); // check if TC bit is set

SPI2->DR = d0;

while ( (SPI2->SR & SPI_SR_TXE) ==0 )
    {

    }

SPI2->DR = d0;

for(;;)
{

if ((USART3->SR & USART_SR_RXNE))
    if (USART3->DR == 0x01)
        break;
}

while ( (SPI2->SR & SPI_SR_TXE) ==0 )
    {
    while(!(USART3->SR & USART_SR_TXE)); // check if TXE bit is set
    USART3->DR = (uint8_t)( (SPI2->SR)>>8 ); // sending a byte
    while(!(USART3->SR & USART_SR_TC)); // check if TC bit is set

    while(!(USART3->SR & USART_SR_TXE)); // check if TXE bit is set
    USART3->DR = (uint8_t)( SPI2->SR); // sending a byte
    while(!(USART3->SR & USART_SR_TC)); // check if TC bit is set
    }


while(!(USART3->SR & USART_SR_TXE)); // check if TXE bit is set
USART3->DR = (uint8_t)( (SPI2->SR)>>8 ); // sending a byte
while(!(USART3->SR & USART_SR_TC)); // check if TC bit is set

while(!(USART3->SR & USART_SR_TXE)); // check if TXE bit is set
USART3->DR = (uint8_t)( SPI2->SR); // sending a byte
while(!(USART3->SR & USART_SR_TC)); // check if TC bit is set

SPI2->DR = d0;

while(!(USART3->SR & USART_SR_TXE)); // check if TXE bit is set
USART3->DR = (uint8_t)( (SPI2->SR)>>8 ); // sending a byte
while(!(USART3->SR & USART_SR_TC)); // check if TC bit is set

while(!(USART3->SR & USART_SR_TXE)); // check if TXE bit is set
USART3->DR = (uint8_t)( SPI2->SR); // sending a byte
while(!(USART3->SR & USART_SR_TC)); // check if TC bit is set

//=============================================================================
// SPI2 Related configuration
//=============================================================================
// enable SPI2 clock
((RCC_TypeDef *) (RCC_BASE))->APB1ENR |= RCC_APB1ENR_SPI2EN;


// configure SPI2
((SPI_TypeDef *) (SPI2_BASE)) -> CR1 |= (SPI_CR1_SPE | SPI_CR1_CPOL |
SPI_CR1_CPHA | SPI_CR1_MSTR |
SPI_CR1_BR_1 | SPI_CR1_SSM | SPI_CR1_SSI);

void __inline init_SPI2(void)
{
SPI2->CR1 =
(0 << SPI_CR1_SPE)
| (0 << SPI_CR1_DFF)
| (1 << SPI_CR1_SSM)
| (1 << SPI_CR1_SSI)
| (1 << SPI_CR1_MSTR)
| (0 << SPI_CR1_BR);

SPI2->CR2 =
(0 << SPI_CR2_RXNEIE)
| (0 << SPI_CR2_TXDMAEN)
| (1 << SPI_CR2_SSOE);

SPI2->CR1 =
(1 << SPI_CR1_SPE)
| (0 << SPI_CR1_DFF)
| (1 << SPI_CR1_SSM)
| (1 << SPI_CR1_SSI)
| (1 << SPI_CR1_MSTR)
| (0 << SPI_CR1_BR);
}

BYTE sd_send_byte(const BYTE data)
{
    BYTE spib;
    while((SPI2->SR & (1 << SPI_SR_TXE)) == 0);
    SPI2->DR = data;
    while((SPI2->SR & (1 << SPI_SR_RXNE)) == 0);
    spib = SPI2->DR;
    return spib;
}

/* SPI1 -- связь с SFM M25PE40
8-bit, MSB first, SPEn, Fpclk2 / 4 (15 MHz), Master, CPOL=0, CPHA=0 */
SPI1->CR1 =
SPI_CR1_CPHA * 0 | // Clock Phase
SPI_CR1_CPOL * 0 | // Clock Polarity
SPI_CR1_MSTR * 1 | // Master Selection
SPI_CR1_BR_0 * 1 | // Baud Rate Control - fpclk2 / 4 = 15 MHz
SPI_CR1_BR_1 * 0 | //
SPI_CR1_BR_2 * 0 | //
SPI_CR1_SPE * 1 | // SPI Enable
SPI_CR1_LSBFIRST * 0 | // Frame Format
SPI_CR1_SSI * 1 | // Internal slave select
SPI_CR1_SSM * 1 | // Software slave management
SPI_CR1_RXONLY * 0 | // Receive only
SPI_CR1_DFF * 0 | // Data Frame Format
SPI_CR1_CRCNEXT * 0 | // Transmit CRC next
SPI_CR1_CRCEN * 0 | // Hardware CRC calculation enable
SPI_CR1_BIDIOE * 0 | // Output enable in bidirectional mode
SPI_CR1_BIDIMODE * 0; // Bidirectional data mode enable
SPI1->CR2 =
SPI_CR2_RXDMAEN * 0 | // Rx Buffer DMA Enable
SPI_CR2_TXDMAEN * 0 | // Tx Buffer DMA Enable
SPI_CR2_SSOE * 0 | // SS Output Enable
SPI_CR2_FRF * 0 | // Protocol format - 0: SPI Motorola mode, 1: SPI TI mode
SPI_CR2_ERRIE * 0 | // Error Interrupt Enable
SPI_CR2_RXNEIE * 0 | // RX buffer Not Empty Interrupt Enable
SPI_CR2_TXEIE * 0; // Tx buffer Empty Interrupt Enable
// SPI1->CR1 |= SPI_CR1_MSTR | SPI_CR1_SPE; // Разрешить, Мастер

/* SPI2 -- конфигурирование EP3C5
CONF_N (NSS) переключается программно */
SPI2->CR1 =
SPI_CR1_CPHA * 0 | // Clock Phase
SPI_CR1_CPOL * 0 | // Clock Polarity
SPI_CR1_MSTR * 1 | // Master Selection
SPI_CR1_BR_0 * 0 | // Baud Rate Control - fpclk1 / 2 = 15 MHz
SPI_CR1_BR_1 * 0 | //
SPI_CR1_BR_2 * 0 | //
SPI_CR1_SPE * 1 | // SPI Enable (раньше включалось позже!)
SPI_CR1_LSBFIRST * 1 | // Frame Format
SPI_CR1_SSI * 1 | // Internal slave select (раньше задавалось!)
SPI_CR1_SSM * 1 | // Software slave management
SPI_CR1_RXONLY * 0 | // Receive only
SPI_CR1_DFF * 0 | // Data Frame Format - 8 bit
SPI_CR1_CRCNEXT * 0 | // Transmit CRC next
SPI_CR1_CRCEN * 0 | // Hardware CRC calculation enable
SPI_CR1_BIDIOE * 0 | // Output enable in bidirectional mode
SPI_CR1_BIDIMODE * 0; // Bidirectional data mode enable
SPI2->CR2 =
SPI_CR2_RXDMAEN * 0 | // Rx Buffer DMA Enable
SPI_CR2_TXDMAEN * 0 | // Tx Buffer DMA Enable
SPI_CR2_SSOE * 0 | // SS Output Enable (все равно используется GPIO?)
SPI_CR2_FRF * 0 | // Protocol format - 0: SPI Motorola mode, 1: SPI TI mode
SPI_CR2_ERRIE * 0 | // Error Interrupt Enable
SPI_CR2_RXNEIE * 0 | // RX buffer Not Empty Interrupt Enable
SPI_CR2_TXEIE * 0; // Tx buffer Empty Interrupt Enable
// SPI2->CR1 |= SPI_CR1_SPE;

/* SPI3 -- регистр управления аналоговыми узлами
8-bit, MSB first, SPEn, Fpclk1 / 2 (15MHz), Master, CPOL=0, CPHA=0
74HC595 SCK - Pos, AD5314 SCK - Neg (изменить CPOL) */
SPI3->CR1 =
SPI_CR1_CPHA * 0 | // Clock Phase
SPI_CR1_CPOL * 0 | // Clock Polarity HC595
SPI_CR1_MSTR * 1 | // Master Selection
SPI_CR1_BR_0 * 0 | // Baud Rate Control - fpclk1 / 2 = 15 MHz
SPI_CR1_BR_1 * 0 | //
SPI_CR1_BR_2 * 0 | //
SPI_CR1_SPE * 1 | // SPI Enable
SPI_CR1_LSBFIRST * 0 | // Frame Format
SPI_CR1_SSI * 1 | // Internal slave select
SPI_CR1_SSM * 1 | // Software slave management
SPI_CR1_RXONLY * 0 | // Receive only
SPI_CR1_DFF * 0 | // Data Frame Format (8 bit)
SPI_CR1_CRCNEXT * 0 | // Transmit CRC next
SPI_CR1_CRCEN * 0 | // Hardware CRC calculation enable
SPI_CR1_BIDIOE * 0 | // Output enable in bidirectional mode
SPI_CR1_BIDIMODE * 0; // Bidirectional data mode enable
SPI3->CR2 =
SPI_CR2_RXDMAEN * 0 | // Rx Buffer DMA Enable
SPI_CR2_TXDMAEN * 0 | // Tx Buffer DMA Enable
SPI_CR2_SSOE * 0 | // SS Output Enable
SPI_CR2_FRF * 0 | // Protocol format - 0: SPI Motorola mode, 1: SPI TI mode
SPI_CR2_ERRIE * 0 | // Error Interrupt Enable
SPI_CR2_RXNEIE * 0 | // RX buffer Not Empty Interrupt Enable
SPI_CR2_TXEIE * 0; // Tx buffer Empty Interrupt Enable