entity main is
Port ( VHOD : in STD_LOGIC;
VIHOD : out STD_LOGIC);
end main;

architecture Behavioral of main is


begin
VIHOD<=VHOD;

end Behavioral;

entity testbanch is
PORT(
        vihod);
end entity;

architecture test of testbanch is
component main
PORT(
        vhod:in std_logic;
          vihod:out std_logic
         );
end component;
signal vhod:std_logic:='0';
begin
D:main
PORT MAP(
        vhod=>vhod,
        vihod=>vihod
       );

vh:process
begin
       wait for 100 us; vhod<=not vhod;
end process;
end test;