-- control register (byte 0)
        if ( mst_byte_we(0) = '1' ) then
          mst_reg(0) <= Bus2IP_Data(7 downto 0);
        end if;
        -- status register (byte 1)
        mst_reg(1)(1) <= mst_cmd_sm_busy;
        if ( mst_byte_we(1) = '1' ) then
          -- allows a clear of the 'Done'/'error'/'timeout'
          mst_reg(1)(0) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8);
          mst_reg(1)(2) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8+2);
          mst_reg(1)(3) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8+3);
        else
          -- 'Done'/'error'/'timeout' from master control state machine
          mst_reg(1)(0)  <= mst_cmd_sm_set_done or mst_reg(1)(0);
          mst_reg(1)(2)  <= mst_cmd_sm_set_error or mst_reg(1)(2);
          mst_reg(1)(3)  <= mst_cmd_sm_set_timeout or mst_reg(1)(3);
        end if;
        -- byte 2 and 3 are reserved
        -- address register (byte 4 to 7)
        -- be register (byte 8 to 9)
        -- length register (byte 12 to 13)
        -- byte 10, 11 and 14 are reserved
        for byte_index in 4 to 14 loop
          if ( mst_byte_we(byte_index) = '1' ) then
            mst_reg(byte_index) <= Bus2IP_Data(
                                     (byte_index-(byte_index/BE_WIDTH)*BE_WIDTH)*8+7 downto
                                     (byte_index-(byte_index/BE_WIDTH)*BE_WIDTH)*8);
          end if;
        end loop;
      end if;

// ------------------------------------------------------
  // Example code to read/write user logic slave model s/w accessible registers
  //
  // Note:
  // The example code presented here is to show you one way of reading/writing
  // software accessible registers implemented in the user logic slave model.
  // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
  // to one software accessible register by the top level template. For example,
  // if you have four 32 bit software accessible registers in the user logic,
  // you are basically operating on the following memory mapped registers:
  //
  //    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
  //                     "1000"   C_BASEADDR + 0x0
  //                     "0100"   C_BASEADDR + 0x4
  //                     "0010"   C_BASEADDR + 0x8
  //                     "0001"   C_BASEADDR + 0xC
  //
  // ------------------------------------------------------

  assign
    slv_reg_write_sel = Bus2IP_WrCE[10:0],
    slv_reg_read_sel  = Bus2IP_RdCE[10:0],
    slv_write_ack     = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9]  || Bus2IP_WrCE[10],
    slv_read_ack      = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9]  || Bus2IP_RdCE[10];

  // implement slave model register(s)
  always @( posedge Bus2IP_Clk )
    begin

      if ( Bus2IP_Resetn == 1'b0 )
        begin
                    fifo_write_signal <= 0;
          command_reg <= 0;
          path_data_reg <= 0;
          start_step_time_reg <= 0;
          max_step_time_reg <= 0;
          min_step_time_reg <= 0;
          step_time_plus_reg <= 0;
          step_time_minus_reg <= 0;
          stop_path_length <= 0;
          step_len <= 0;
                    dir_len <= 0;
                    STATUS_ADDR <= MAIN_STATUS;
        end
      else
                begin
                    //сбрасываем флаг если нет сигнала записи в данные пути
                    if(slv_reg_write_sel !=  11'b0000000010)
                        fifo_write_signal <= 2'b00;    

                    case ( slv_reg_write_sel )
                        STATUS_REG_CE : //запись в регистр статуса - выбор регистра
                            begin
                                if ( Bus2IP_BE[0] == 1 ) //только младший байт
                                    STATUS_ADDR <=  Bus2IP_Data[STATUS_ADR_SIZE - 1 : 0];
                            end
                        COMMAND_REG_CE :
                            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                                if ( Bus2IP_BE[byte_index] == 1 )
                                    command_reg[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
                        PATH_DATA_REG_CE :
                            begin
                                for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                                    if ( Bus2IP_BE[byte_index] == 1 )
                                        path_data_reg[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
                                
                                //по клоку надо выдать строб на запись в фифо
                                if(fifo_write_signal == 0)
                                    fifo_write_signal <= 2'b01;
                                //по следующему клоку надо снять строб, но не поставить заново если будет еще клок
                                else if (fifo_write_signal == 2'b01)
                                    fifo_write_signal <= 2'b10;
                                //когда убиреться разрешение на запись, флаг сброситься в 0    
                            end            
                        START_STEP_REG_CE :
                            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                                if ( Bus2IP_BE[byte_index] == 1 )
                                    start_step_time_reg[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
                        MAX_STEP_REG_CE :
                            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                                if ( Bus2IP_BE[byte_index] == 1 )
                                    max_step_time_reg[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
                        MIN_STEP_REG_CE :
                            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                                if ( Bus2IP_BE[byte_index] == 1 )
                                    min_step_time_reg[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
                        PLUS_STEP_REG_CE :
                            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                                if ( Bus2IP_BE[byte_index] == 1 )
                                    step_time_plus_reg[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
                        MINUS_STEP_REG_CE :
                            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                                if ( Bus2IP_BE[byte_index] == 1 )
                                    step_time_minus_reg[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
                        STOP_PATH_REG_CE :
                            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                                if ( Bus2IP_BE[byte_index] == 1 )
                                    stop_path_length[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
                        STEP_LEN_REG_CE :
                            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                                if ( Bus2IP_BE[byte_index] == 1 )
                                    step_len[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
                        STEP_DIR_REG_CE :
                            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                                if ( Bus2IP_BE[byte_index] == 1 )
                                    dir_len[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
                        default :
                            begin
                            end
                    endcase
                end    
    end // SLAVE_REG_WRITE_PROC

  // implement slave model register read mux
  always @( slv_reg_read_sel or status_reg or command_reg or path_data_reg or start_step_time_reg or max_step_time_reg or min_step_time_reg or step_time_plus_reg or step_time_minus_reg or stop_path_length or step_len or dir_len)
    begin
      case ( slv_reg_read_sel )
        STATUS_REG_CE : slv_ip2bus_data <= status_reg;
        COMMAND_REG_CE : slv_ip2bus_data <= command_reg;
        PATH_DATA_REG_CE : slv_ip2bus_data <= path_data_reg;
        START_STEP_REG_CE : slv_ip2bus_data <= start_step_time_reg;
        MAX_STEP_REG_CE : slv_ip2bus_data <= max_step_time_reg;
        MIN_STEP_REG_CE : slv_ip2bus_data <= min_step_time_reg;
        PLUS_STEP_REG_CE : slv_ip2bus_data <= step_time_plus_reg;
        MINUS_STEP_REG_CE : slv_ip2bus_data <= step_time_minus_reg;
        STOP_PATH_REG_CE : slv_ip2bus_data <= stop_path_length;
        STEP_LEN_REG_CE : slv_ip2bus_data <= step_len;
                STEP_DIR_REG_CE : slv_ip2bus_data <= dir_len;
        default : slv_ip2bus_data <= 0;
      endcase

    end // SLAVE_REG_READ_PROC

//  ------------------------------------------
// Example code to demonstrate user logic master model functionality
//
// Note:
// The example code presented here is to show you one way of instatiating
// the AXI4 (Burst) master interface under user control. It is provided for
// demonstration purposes only and allows the user to exercise the AXI4 (Burst)
// master interface during test and evaluation of the template.
// This user logic master model contains a 16-byte flattened register and
// the user is required to initialize the value to desire and then write to
// the model's 'Go' port to initiate the user logic master operation.
//
//    Control Register     (C_BASEADDR + OFFSET + 0x0):
//       bit 0    - Rd     (Read Request Control)
//       bit 1    - Wr     (Write Request Control)
//       bit 2    - BL     (Bus Lock Control)
//       bit 3    - Brst   (Burst Assertion Control)
//       bit 4-7  - Spare  (Spare Control Bits)
//    Status Register      (C_BASEADDR + OFFSET + 0x1):
//       bit 0    - Done   (Transfer Done Status)
//       bit 1    - Busy   (User Logic Master is Busy)
//       bit 2    - Error  (User Logic Master request got error response)
//       bit 3    - Tmout  (User Logic Master request is timeout)
//       bit 2-7  - Spare  (Spare Status Bits)
//    Addrress Register    (C_BASEADDR + OFFSET + 0x4):
//       bit 0-31 - Target Address (This 32-bit value is used to populate the
//                  ip2bus_Mst_Addr(0:31) address bus during a Read or Write
//                  user logic master operation)
//    Byte Enable Register (C_BASEADDR + OFFSET + 0x8):
//       bit 0-15 - Master BE (This 16-bit value is used to populate the
//                  ip2bus_Mst_BE byte enable bus during a Read or Write user
//                  logic master operation for single data beat transfer)
//    Length Register      (C_BASEADDR + OFFSET + 0xC):
//       bit 0-3  - Reserved
//       bit 4-15 - Transfer Length (This 12-bit value is used to populate the
//                  ip2bus_Mst_Length(0:11) transfer length bus which specifies
//                  the number of bytes (1 to 4095) to transfer during user logic
//                  master Read or Write fixed length burst operations)
//    Go Register          (C_BASEADDR + OFFSET + 0xF):
//       bit 0-7  - Go Port (Write to this byte address initiates the user
//                  logic master transfer, data key value of 0x0A must be used)
//
//    Note: OFFSET may be different depending on your address space configuration,
//          by default it's 0x100. Refer to IPIF address range array
//          for actual value.
//
// Here's an example procedure in your software application to initiate a 64-byte
// read operation (single data beat) of this master model:
//    1. write 0x09 to the control register to perform write operation.
//    2. write the target address to the address register.
//    3. write valid byte lane value to the be register
//      - note: this value must be aligned with ip2bus address  
//    4. write 0x040 to the length register
//    5. write 0x0a to the go register, this will start the master write operation
//
// Here's an example procedure in your software application to initiate a 64-byte
// write operation (single data beat) of this master model:
//   1. write 0x0A to the control register to perform write operation.
//   2. write the target address to the address register
//   3. write valid byte lane value to the be register
//      - note: this value must be aligned with ip2bus address
//   4. write 0x0040 to the length register
//   5. write 0x0a to the go register, this will start the master write operation
//
//----------------------------------------
  assign mst_reg_write_req = Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13];
  assign mst_reg_read_req  = Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13];
  assign mst_reg_write_sel = Bus2IP_WrCE[13 : 10];
  assign mst_reg_read_sel  = Bus2IP_RdCE[13 : 10];
  assign mst_write_ack     = mst_reg_write_req;
  assign mst_read_ack      = mst_reg_read_req;

  // rip control bits from master model registers
  assign mst_cntl_rd_req   = mst_reg[0][0];
  assign mst_cntl_wr_req   = mst_reg[0][1];
  assign mst_cntl_bus_lock = mst_reg[0][2];
  assign mst_cntl_burst    = mst_reg[0][3];
  assign mst_ip2bus_addr   = {mst_reg[7], mst_reg[6], mst_reg[5], mst_reg[4]};
  assign mst_ip2bus_be     = {mst_reg[9], mst_reg[8]};
  assign mst_xfer_reg_len  = {mst_reg[14][3 : 0], mst_reg[13], mst_reg[12]};// changed to 20 bits
  assign mst_xfer_length   = mst_xfer_reg_len[C_LENGTH_WIDTH-1 : 0];

  // implement byte write enable for each byte slice of the master model registers
  always @ (Bus2IP_BE or mst_reg_write_req or mst_reg_write_sel)
    begin
      for ( byte_index = 0; byte_index <= 15; byte_index = byte_index+1 )
        mst_byte_we[byte_index] <= mst_reg_write_req & mst_reg_write_sel[3 - (byte_index/BE_WIDTH)] & Bus2IP_BE[byte_index - ((byte_index/BE_WIDTH)*BE_WIDTH)];
    end // MASTER_REG_BYTE_WR_EN
  // implement master model registers
  // The master registers are written to initialize master transfer.
  always @ ( posedge Bus2IP_Clk)
    begin
    if (Bus2IP_Resetn == 1'b0 )
      begin
        for ( byte_index = 0; byte_index <= 14; byte_index = byte_index+1 )
          mst_reg[byte_index] <= 0;
      end
    else
      begin
          if ( mst_byte_we[0] == 1'b1 )
            begin
              mst_reg[0][7:0] <= Bus2IP_Data[7 : 0];
            end
          
             mst_reg[1][1] <= mst_cmd_sm_busy;  
      
          if (mst_byte_we[1] == 1'b1 )
          // allows a clear of the 'Done'/'error'/'timeout'
            begin
              mst_reg[1][0] <= Bus2IP_Data[(1-(1/BE_WIDTH)*BE_WIDTH)*8];
              mst_reg[1][2] <= Bus2IP_Data[(1-(1/BE_WIDTH)*BE_WIDTH)*8+2];
              mst_reg[1][3] <= Bus2IP_Data[(1-(1/BE_WIDTH)*BE_WIDTH)*8+3];
            end
        else
          // 'Done'/'error'/'timeout' from master control state machine
          begin
             mst_reg[1][0]  <= mst_cmd_sm_set_done | mst_reg[1][0];
             mst_reg[1][2]  <= mst_cmd_sm_set_error | mst_reg[1][2];
             mst_reg[1][3]  <= mst_cmd_sm_set_timeout | mst_reg[1][3];
           end
             // byte 2 and 3 are reserved
             // address register (byte 4 to 7)
             // be register (byte 8 to 9)
             // length register (byte 12 to 13)
             // byte 10, 11 and 14 are reserved
         for ( byte_index = 4; byte_index <= 14; byte_index = byte_index+1 )
           if ( mst_byte_we[byte_index] == 1'b1 )
             begin
               mst_reg[byte_index] <= Bus2IP_Data[(byte_index-(byte_index/BE_WIDTH)*BE_WIDTH)*8 +: 8];
             end
      end
    end // MASTER_REG_WRITE_PROC

STEP_LEN_REG_CE :
                            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
                                if ( Bus2IP_BE[byte_index] == 1 )
                                    step_len[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];

//----------------------------------------------------------------------------
// Ethernet
//----------------------------------------------------------------------------

//----------------------------------------------------------------------------
// TX PHY physical interface interface
//----------------------------------------------------------------------------

wire [7:0] gmii_txd;
wire gmii_tx_en;
wire gmii_tx_er;

always @(posedge clk_125M_tx) begin
    ETHERNET_TXD <= gmii_txd;
    ETHERNET_TX_EN <= gmii_tx_en;
    ETHERNET_TX_ER <= gmii_tx_er;
end    

ODDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"),
    .INIT(1'b0),
    .SRTYPE("SYNC")
) ODDR_inst (
      .Q(ETHERNET_TX_CLK),
      .C(clk_125M_tx),
      .CE(1'b1),
      .D1(1'b0),
      .D2(1'b1),
      .R(1'b0),
      .S(1'b0)
);

//----------------------------------------------------------------------------
// RX PHY physical interface interface
//----------------------------------------------------------------------------

wire clk_125M_rx_io;

BUFIO BUFIO_inst (.I(ETHERNET_RX_CLK), .O(clk_125M_rx_io));
BUFG BUFG_inst (.I(ETHERNET_RX_CLK), .O(clk_125M_rx));

reg [7:0] gmii_rxd;
reg gmii_rx_dv;
reg gmii_rx_er;

always @(posedge clk_125M_rx_io) begin
    gmii_rxd <= ETHERNET_RXD;
    gmii_rx_dv <= ETHERNET_RX_DV;
    gmii_rx_er <= ETHERNET_RX_ER;
end    

//----------------------------------------------------------------------------
// Core itself
//----------------------------------------------------------------------------

wire mac_tx_reset;
reset_sync rsync_mac_tx(.clk(clk_125M_tx), .areset(1'b0), .reset(mac_tx_reset), .resetn());

wire mac_rx_reset;
reset_sync rsync_mac_rx(.clk(clk_125M_rx), .areset(1'b0), .reset(mac_rx_reset), .resetn());

wire [79:0] tx_mac_config_vector = {64'b0, 15'b0010_0000_0000_001, mac_tx_reset};
wire [79:0] rx_mac_config_vector = {64'b0, 15'b0010_0000_0000_001, mac_rx_reset};

tri_mode_eth_mac tri_mode_eth_mac (
    .glbl_rstn(1'b1),
    .rx_axi_rstn(1'b1),
    .tx_axi_rstn(1'b1),
    .rx_axi_clk(clk_125M_rx),
    .rx_reset_out(),
    .rx_axis_mac_tdata(),
    .rx_axis_mac_tvalid(),
    .rx_axis_mac_tlast(),
    .rx_axis_mac_tuser(),
    .rx_statistics_vector(),
    .rx_statistics_valid(),
    .tx_axi_clk(clk_125M_tx),
    .tx_reset_out(),
    .tx_axis_mac_tdata(eth_axis_tdata),
    .tx_axis_mac_tvalid(eth_axis_tvalid),
    .tx_axis_mac_tlast(eth_axis_tlast),
    .tx_axis_mac_tuser(1'b0),
    .tx_axis_mac_tready(eth_axis_tready),
    .tx_ifg_delay(8'b0),
    .tx_statistics_vector(),
    .tx_statistics_valid(),
    .pause_req(1'b0),
    .pause_val(16'b0),
    .speed_is_100(),
    .speed_is_10_100(),
    .gmii_txd(gmii_txd),
    .gmii_tx_en(gmii_tx_en),
    .gmii_tx_er(gmii_tx_er),
    .gmii_rxd(gmii_rxd),
    .gmii_rx_dv(gmii_rx_dv),
    .gmii_rx_er(gmii_rx_er),
    .rx_mac_config_vector(rx_mac_config_vector), // input [79 : 0] rx_mac_config_vector
    .tx_mac_config_vector(tx_mac_config_vector) // input [79 : 0] tx_mac_config_vector
);