On CC112x the ADC in the receive path is a single bit sigma delta.

Option 1: For conceptual testing it is possible to get the data on GPIO pins, see table 10 in the UserGuide (http://www.ti.com/lit/ug/swru295d/swru295d.pdf) GPIOx_CFG=46. Due to the high frequency nature of the output signals using this method will likely reduce the sensitivity some due to the noise created by the IOs.


Option2: LVDS: CC112x contains a LVDS interface where it is possible to output the I and Q data without reduce sensitivity.

For CC112x devices the LVDS data is available on GPIO2 and GPIO3 pins, which can be connected to the LVDS receiver inputs, for instance LVDS input on a FPGA. In addition it is important to add common ground between the CC112x and LVDS receiver, and avoid any kind of ground current loops.



The highest LVDS data speed is 64 MHz for CC1120 and 80 MHz for CC1125 (i.e. two times the crystal frequency) thus it is important that the board is designed as transmission lines with characteristic impedance of 100ohm for 64-80 MHz frequency. The LVDS format is [I 1 Q 0].



Please design PCB with the possibility of having a 100 ohm external termination close to CC112x and close to the external LVDS receiver.



To activate the LVDS interface set the following registers:



IOCCFG3 0xB0
IOCCFG2 0xB0
IOCCFG1 0xB0
IOCCFG0 0xB0



Comment: Register setting for setting the output Pad’s in analogue transfer mode and digital drivers are set to high impedance.



ADC_TEST 0x20
ATEST 0x00
ATEST_LVDS 0x02



Comment: Registers setting for selecting IF-ADC data on LVDS interface.

Option 1: For conceptual testing it is possible to get the data on GPIO pins, see table 10 in the UserGuide (http://www.ti.com/lit/ug/swru295d/swru295d.pdf) GPIOx_CFG=46. Due to the high frequency nature of the output signals using this method will likely reduce the sensitivity some due to the noise created by the IOs.


Option2: LVDS: CC112x contains a LVDS interface where it is possible to output the I and Q data without reduce sensitivity.

For CC112x devices the LVDS data is available on GPIO2 and GPIO3 pins, which can be connected to the LVDS receiver inputs, for instance LVDS input on a FPGA. In addition it is important to add common ground between the CC112x and LVDS receiver, and avoid any kind of ground current loops.



The highest LVDS data speed is 64 MHz for CC1120 and 80 MHz for CC1125 (i.e. two times the crystal frequency) thus it is important that the board is designed as transmission lines with characteristic impedance of 100ohm for 64-80 MHz frequency. The LVDS format is [I 1 Q 0].



Please design PCB with the possibility of having a 100 ohm external termination close to CC112x and close to the external LVDS receiver.



To activate the LVDS interface set the following registers:



IOCCFG3 0xB0
IOCCFG2 0xB0
IOCCFG1 0xB0
IOCCFG0 0xB0



Comment: Register setting for setting the output Pad’s in analogue transfer mode and digital drivers are set to high impedance.



ADC_TEST 0x20
ATEST 0x00
ATEST_LVDS 0x02



Comment: Registers setting for selecting IF-ADC data on LVDS interface.