create_clock -period 20 [get_ports OSC_50[0]]
create_clock -period 20 [get_ports OSC_50[1]]
create_clock -period 20 [get_ports OSC_50[2]]

create_clock -period 10 [get_ports ADA_DCO]
create_clock -period 10 [get_ports FPGA_CLK_A_P]
create_clock -period 10 [get_ports FPGA_CLK_A_N]
#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks

# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty

module adc
(
OSC_50,
ADA_DCO,
AD,
DA,
FPGA_CLK_A_N,
FPGA_CLK_A_P,
ADA_OE,
ADA_SPI_CS,
J1_152,
XT_IN_N,
XT_IN_P
);

input [2:0] OSC_50;
input ADA_DCO;
input [13:0] AD;
inout FPGA_CLK_A_N;
inout FPGA_CLK_A_P;
output ADA_OE;
output ADA_SPI_CS;


wire sys_clk;
wire sys_clk_90deg;
wire sys_clk_180deg;
wire sys_clk_270deg;
wire pll_locked;

reg [13:0] per_a2da_d;
reg [13:0] ddd;

assign ADA_OE = 1'b0; // enable ADA output

assign ADA_SPI_CS = 1'b1; // disable ADA_SPI_CS (CSB)

inout J1_152;
input XT_IN_N;
input XT_IN_P;

output [13:0] DA;
assign FPGA_CLK_A_N = ~sys_clk_180deg;
assign FPGA_CLK_A_P = sys_clk_180deg;
//assign FPGA_CLK_B_P = sys_clk_270deg;
//assign FPGA_CLK_B_N = ~sys_clk_270deg;

//--- pll
pll pll_inst(
.inclk0(OSC_50[0]),
.c0(sys_clk),
.c1(sys_clk_90deg),
.c2(sys_clk_180deg),
.c3(sys_clk_270deg),
.locked(pll_locked)
);

always @(posedge ADA_DCO)
begin
per_a2da_d <= AD;
end

assign DA = ddd;

always @(posedge sys_clk)
begin
ddd <= per_a2da_d;
end
endmodule