library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity sinnw is  
  port ( clk   : in  std_logic; en    : in  std_logic; preset : in  std_logic; adr : in std_logic_vector(1 downto 0);
    sin_reg : in std_logic_vector(15 downto 0);    sine   : out std_logic_vector(13 downto 0));
end sinnw;
architecture behave_sine_cos of sinnw is
    signal sine_s : unsigned(13 downto 0); signal ampl : integer; signal cosw : natural; signal shft : natural;
begin  -- behave_sine_cos
registers: process (clk, en)
    variable sine_d : integer;
    variable y_1, y_2, sine_m : integer;

begin  -- process registers
  if clk'event and clk = '1' then    -- rising clock edge
    if (en = '1') then
      sine_d := cosw*y_1;
      sine_m := sine_d/4096-y_2;
      y_2 := y_1;      
      y_1 := sine_m;
      sine_s <= to_unsigned(sine_m+ shft,14);
      sine <= std_logic_vector(sine_s);
    else
        y_1 := 0;
        y_2 := ampl;
        sine <= "00000000000000";
    end if;
  end if;
end process registers;

setregisters: process (clk, preset)
begin  -- preset registers
  if clk'event and clk = '1' then    -- rising clock edge
    if (preset = '1') then
        CASE adr IS
            WHEN  "00"  =>  ampl <= to_integer(signed(sin_reg));
            WHEN  "01"  =>  cosw <= to_integer(unsigned(sin_reg));
            WHEN OTHERS =>  shft <= to_integer(unsigned(sin_reg));
        END CASE;
    end if;
  end if;
end process setregisters;

end behave_sine_cos;