// Copyright (C) 2009 OutputLogic.com
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED    
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//-----------------------------------------------------------------------------
// CRC module for data[7:0] ,   crc[15:0]=1+x^2+x^15+x^16;
//-----------------------------------------------------------------------------

module CRC( data_in, crc_en, crc_out,rst, clk, countbytes);
//---------------------------------------------------------------------//
//---------------------------------------------------------------------//
input [7:0] data_in;
input crc_en,rst, clk;
output [15:0] crc_out;
output[7:0] countbytes;
//---------------------------------------------------------------------//
//---------------------------------------------------------------------//
  reg [15:0] lfsr_q,lfsr_c;
  reg [7:0] countbytes_reg;
//---------------------------------------------------------------------//
//---------------------------------------------------------------------//
  assign crc_out = lfsr_q;
  assign countbytes = countbytes_reg;
//---------------------------------------------------------------------//
//---------------------------------------------------------------------//

  assign crc_out = lfsr_q;

  always @(posedge clk, posedge rst) begin
    if(rst) begin
      lfsr_q = {16{1'b1}};
        countbytes_reg = 0;
    end
    else begin
    
        if(crc_en)
        begin        
            lfsr_c[0] = lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[7];
            lfsr_c[1] = lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[7];
            lfsr_c[2] = lfsr_q[8] ^ lfsr_q[9] ^ data_in[0] ^ data_in[1];
            lfsr_c[3] = lfsr_q[9] ^ lfsr_q[10] ^ data_in[1] ^ data_in[2];
            lfsr_c[4] = lfsr_q[10] ^ lfsr_q[11] ^ data_in[2] ^ data_in[3];
            lfsr_c[5] = lfsr_q[11] ^ lfsr_q[12] ^ data_in[3] ^ data_in[4];
            lfsr_c[6] = lfsr_q[12] ^ lfsr_q[13] ^ data_in[4] ^ data_in[5];
            lfsr_c[7] = lfsr_q[13] ^ lfsr_q[14] ^ data_in[5] ^ data_in[6];
            lfsr_c[8] = lfsr_q[0] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[6] ^ data_in[7];
            lfsr_c[9] = lfsr_q[1] ^ lfsr_q[15] ^ data_in[7];
            lfsr_c[10] = lfsr_q[2];
            lfsr_c[11] = lfsr_q[3];
            lfsr_c[12] = lfsr_q[4];
            lfsr_c[13] = lfsr_q[5];
            lfsr_c[14] = lfsr_q[6];
            lfsr_c[15] = lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[7];

            countbytes_reg = countbytes_reg +1;    
            lfsr_q  = lfsr_c;
        end
        else begin
        
            lfsr_q  = lfsr_q;
        end    
            
      
    end
  end // always



endmodule // crc
//---------------------------------------------------------------------//
//---------------------------------------------------------------------//

//-----------------------------------------------------------------------------
// Copyright (C) 2009 OutputLogic.com
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED    
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//-----------------------------------------------------------------------------
// CRC module for data[7:0] ,   crc[15:0]=1+x^13+x^15+x^16;
//-----------------------------------------------------------------------------
module crc_modbus(
  input [7:0] data_in,
  input crc_en,
  output [15:0] crc_out,
  input rst,
  input clk);

  reg [15:0] lfsr_q,lfsr_c;

  assign crc_out = lfsr_q;

  always @(*) begin
    lfsr_c[0] = lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[12] ^ lfsr_q[15] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[4] ^ data_in[7];
    lfsr_c[1] = lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[13] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[5];
    lfsr_c[2] = lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[14] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[6];
    lfsr_c[3] = lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[15] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[7];
    lfsr_c[4] = lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ^ data_in[4] ^ data_in[5] ^ data_in[6];
    lfsr_c[5] = lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[5] ^ data_in[6] ^ data_in[7];
    lfsr_c[6] = lfsr_q[14] ^ lfsr_q[15] ^ data_in[6] ^ data_in[7];
    lfsr_c[7] = lfsr_q[15] ^ data_in[7];
    lfsr_c[8] = lfsr_q[0];
    lfsr_c[9] = lfsr_q[1];
    lfsr_c[10] = lfsr_q[2];
    lfsr_c[11] = lfsr_q[3];
    lfsr_c[12] = lfsr_q[4];
    lfsr_c[13] = lfsr_q[5] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[12] ^ lfsr_q[15] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[4] ^ data_in[7];
    lfsr_c[14] = lfsr_q[6] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[13] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[5];
    lfsr_c[15] = lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[11] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[0] ^ data_in[1] ^ data_in[3] ^ data_in[6] ^ data_in[7];

  end // always

  always @(posedge clk, posedge rst) begin
    if(rst) begin
      lfsr_q <= {16{1'b1}};
    end
    else begin
      lfsr_q <= crc_en ? lfsr_c : lfsr_q;
    end
  end // always
endmodule // crc

always @(posedge clk, posedge rst) begin
    if(rst) begin
      lfsr_q <= {16{1'b1}};
    end
    else begin
      lfsr_q <= crc_en ? lfsr_c : lfsr_q;
    end
  end // always

        {
            int crc = 0xFFFF;
            byte[] msg = new byte[6];
            msg[0] = 0x24;
            msg[1] = 0x08;
            msg[2] = 0x00;
            msg[3] = 0x00;
            msg[4] = 0x00;
            msg[5] = 0x00;

            for (int j = 0; j < 6; j++)
            {
              

                crc = crc ^ msg[j];

                for (int i = 0; i < 8; i++)
                {

                    bool ff =  (crc & 1)==1;
                    crc = crc >> 1;

                    if (ff)
                    {
                        crc = crc ^ 0xA001;
                    }                    

                }
              
            }
        }

//---------------------------------------------------------------------//
//---------------------------------------------------------------------//
module crc_mobus(input clck, input datacrcini,input datacrcnew, input[7:0]datain, output[15:0] crcout, output crcrd);
//---------------------------------------------------------------------//
//---------------------------------------------------------------------//
reg[15:0] countcrc      = 0;
reg[3:0] counterbytes   = 0;
reg[3:0] statucountcrc  = 0;

reg crcrdy     = 0;
reg loaddata   = 0;
reg bitlsb     = 0;
//---------------------------------------------------------------------//
//---------------------------------------------------------------------//
always @(posedge clck)
begin
    if(datacrcini)
    begin
        
        crcrdy          = 0;
        loaddata        = 0;
        statucountcrc   = 0;
        counterbytes    = 0;    
        countcrc[15:0]  = 16'b1111111111111111;
    end
    else if(datacrcnew) begin    
        if(loaddata == 0)
        begin
            loaddata      = 1;    
            crcrdy        = 0;
            counterbytes  = 0;                        
            countcrc[15:0] = {8'b00000000,datain[7:0]} ^countcrc[15:0];
            statucountcrc = 0;
        end
    end
    else begin        
        
        if(counterbytes < 8)
        begin
        
            case(statucountcrc)
            0:
            begin
                bitlsb = countcrc[0];
                statucountcrc = 1;
            end
            
            1:
            begin    
                countcrc  = countcrc>>1;                
                statucountcrc = 2;
            end
            
            2:
            begin
                if(bitlsb)
                begin
                    countcrc = countcrc ^ 16'b 1010000000000001;
                end                
                counterbytes  = counterbytes +1;
                statucountcrc = 0;                
            end
            
            default:
            begin
                statucountcrc = 0;
            end
            endcase    
            
        end
        else begin                
            crcrdy = 1;
            loaddata = 0;
        end
        
    end
    
end
//---------------------------------------------------------------------//
//---------------------------------------------------------------------//

assign crcout = countcrc;
assign crcrd  = crcrdy;
    
endmodule