void PwmInit(void)
{
//ch1 -PA0
GPIOA->CRL |= GPIO_CRL_MODE0; //50Mhz
GPIOA->CRL &= ~GPIO_CRL_CNF0; //clear CNF[1:0] for PA0
GPIOA->CRL |= GPIO_CRL_CNF1_0; //output Push-Pull in alternative function mode
//ch2 - PA1
GPIOA->CRL |= GPIO_CRL_MODE1; //50Mhz
GPIOA->CRL &= ~GPIO_CRL_CNF1; //clear CNF[1:0] for PA1
GPIOA->CRL |= GPIO_CRL_CNF1_1; //output Push-Pull in alternative function mode
//ch3 - PA2
GPIOA->CRL |= GPIO_CRL_MODE2; //50Mhz
GPIOA->CRL &= ~GPIO_CRL_CNF2; //clear CNF[1:0] for PA2
GPIOA->CRL |= GPIO_CRL_CNF2_1; //output Push-Pull in alternative function mode
//ch4 - PA3
GPIOA->CRL |= GPIO_CRL_MODE3; //50Mhz
GPIOA->CRL &= ~GPIO_CRL_CNF3; //clear CNF[1:0] for PA3
GPIOA->CRL |= GPIO_CRL_CNF3_1; //output Push-Pull in alternative function mode
//TIM2 Settings
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
TIM2->CR1 |= TIM_CR1_ARPE; //autorelode mode
TIM2->CCMR1 |= TIM_CCMR1_OC1PE | TIM_CCMR1_OC2PE; //Output Compare Preload enable
TIM2->CCMR2 |= TIM_CCMR2_OC3PE | TIM_CCMR2_OC4PE;
TIM2->ARR = 20000;
TIM2->CCR1 = 10000; //ch1 1duty cycle = 50%
TIM2->CCR2 = 10000; //ch2 1duty cycle = 50%
TIM2->CCR3 = 10000; //ch2 1duty cycle = 50%
TIM2->CCR4 = 10000; //ch2 1duty cycle = 50%
//TIM2->CCER |= TIM_CCER_CC2P; //polarity of output signal
//Capture/Compare output enable
TIM2->CCER |= TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E;
//Output Compare Mode - 110 - PWM mode 1
TIM2->CCMR1 |= (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1);
TIM2->CCMR1 |= (TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1);
TIM2->CCMR2 |= (TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1);
TIM2->CCMR2 |= (TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1);
TIM2->CR1 |= TIM_CR1_CEN; //start counting
}

GPIOA->CRL |= GPIO_CRL_CNF1_0; //output Push-Pull in alternative function mode