Place:1355 - Component < MDO/MCD/blk00003926 > is driven by DCM or PLL
   component < MCM/pll_base_inst/PLL_ADV > placed at < PLL_ADV_X0Y2 >. This
   requires the load component to be range constrained to CLOCKREGION_X0Y5 or
   CLOCKREGION_X1Y5. Placer was not able to apply this range constraint because
   component < MDO/MCD/blk00003926 > has a LOC constraint or area group in a
   different clock region. Please check whether the user constraints and remove
   any conflicting LOCs or area groups. Note that the loads of a DCM/PLL must be
   constrained to the two adjacent clock regions to the DCM/PLL. Using DCM/PLL
   clocks to drive clock pins directly is not a recommended practice. Using a
   BUFG will give more flexibility to the placer and produce superior placement
   results.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
----------------------------------------------------------------------------------------------------
entity MODULE_MAIN is
    Port (
        G_CLK_IN          : in  STD_LOGIC;    
        G_TX_DATA_OUT     : out STD_LOGIC_VECTOR (3 downto 0);
        G_TX_EN_OUT       : out STD_LOGIC;
        G_TX_ER_OUT       : out STD_LOGIC;
        G_TX_CLK_IN       : in  STD_LOGIC;
        G_RES_ETH_OUT     : out STD_LOGIC;
        G_MD_CLK_OUT      : out STD_LOGIC;
        G_MD_IO_OUT       : out STD_LOGIC;
        data_p            : in  STD_LOGIC_VECTOR (15 downto 0); --    
        data_n            : in  STD_LOGIC_VECTOR (15 downto 0); --            
        G_CLK_ADC_P_IN    : in  STD_LOGIC; --    
        G_CLK_ADC_N_IN    : in  STD_LOGIC; --    
        G_TX_OUT          : out STD_LOGIC :='1';
        G_TEST_TX_OUT     : out STD_LOGIC_VECTOR (2 downto 0)
    );
end MODULE_MAIN;
---------------------------------------------------------------------------------
architecture Behavioral of MODULE_MAIN is
------------------------------------------------------------------------
    component MODULE_CLOCK_MANAGER
        port(
            CLK_IN1    : in  std_logic;
            CLK_OUT1   : out std_logic;
            CLK_OUT2   : out std_logic;
            LOCKED     : out std_logic
        );
    end component;
--------------------------------------------------------------------------
    COMPONENT MD_CLOCK
        Port (
            clk   : in  STD_LOGIC:='0';
            mdclk : out STD_LOGIC:='0';
            mdio  : out STD_LOGIC:='0'
        );
    END COMPONENT;
--------------------------------------------------------------------------------------
    COMPONENT MODULE_SYNCHRONIZATION
        Port (
            CLK_IN   : IN  STD_LOGIC;
            PWR_EN   : IN  std_logic;
            EN_OUT   : out STD_LOGIC;
            PWR_OUT  : out STD_LOGIC;
            TEST     : out STD_LOGIC_VECTOR(2 downto 0)
        );
    END COMPONENT;
--------------------------------------------------------------------------------------
    COMPONENT MODULE_DATA_OUT
        Port (
            CLK         : in  STD_LOGIC;
            TX_CLK      : in  STD_LOGIC;
            DATA_IN_RE  : in  STD_LOGIC_VECTOR (47 downto 0);
            DATA_IN_IM  : in  STD_LOGIC_VECTOR (47 downto 0);
            DATA_IN_EN  : in  STD_LOGIC;
            gtx_data    : out STD_LOGIC_VECTOR (3 downto 0);
            gtx_en      : out STD_LOGIC;
            gtx_er      : out STD_LOGIC
        );
    end COMPONENT;
------------------------------------------------------------------------
    signal clk_125MHz   : std_logic := '0';
    signal data_from_adc    : STD_LOGIC_VECTOR(47 downto 0):=(others=>'0');
    signal clk_from_adc    : STD_LOGIC;
    signal enable    : STD_LOGIC:= '0';
    signal adc_ready : STD_LOGIC:= '0';
    signal ENPWR     : STD_LOGIC:= '0';
    -------- MM RE --------------------------------------------------------------------
begin
--------------------------------------------------------------------------
    MODULE_CLOCK_MGR: MODULE_CLOCK_MANAGER  port map(G_CLK_IN,clk_125MHz,clk_10MHz,G_RES_ETH_OUT);
    MODULE_MD_CLK:  MD_CLOCK  PORT MAP(clk_125MHz, G_MD_CLK_OUT, G_MD_IO_OUT);
---------------------------------------------------------------------------
    ibufds_clk_inst : IBUFGDS generic map (diff_term => true,IOSTANDARD => "LVDS_33") port map (I => G_CLK_ADC_P_IN,IB => G_CLK_ADC_N_IN,O => clk_from_adc);
--------------------input signal-------------------------------------------
    pins: for N in 0 to 15 generate
    begin
        ibufds_inst : IBUFDS generic map (DIFF_TERM  => true,IOSTANDARD => "LVDS_33") port map (I => data_p(N),IB => data_n(N),O => data_from_adc(N));
    end generate;
---------------------------------------------------------------------------
    MSNC: MODULE_SYNCHRONIZATION PORT MAP(clk_125MHz,ENPWR,enable,G_TX_OUT,G_TEST_TX_OUT); --
-----------------------------------------------------------------------------------------
    MDO:MODULE_DATA_OUT Port map(clk_125MHz,G_TX_CLK_IN,
                                         data_from_adc,enable,
                                          G_TX_DATA_OUT,G_TX_EN_OUT,G_TX_ER_OUT
                                          );
-----------------------------------------------------------------------------
end Behavioral;

NET "G_CLK_IN" TNM_NET = "G_CLK_IN";
TIMESPEC TS_G_CLK_IN = PERIOD "G_CLK_IN" 8 ns;
####################################################################
NET "G_CLK_IN" LOC = AA12 |IOSTANDARD = LVCMOS33;#LVCMOS18;
################# ADC CLOCK ####################################################
NET "G_CLK_ADC_P_IN" TNM_NET = "G_CLK_ADC_P_IN";
TIMESPEC TS_G_CLK_ADC_P_IN = PERIOD "G_CLK_ADC_P_IN" 8 ns HIGH 50 %;
NET "G_CLK_ADC_P_IN" LOC = B12 |IOSTANDARD = LVDS_33;
################# ADC DATA #########################################
NET "data_p[0]"  LOC = E16 | IOSTANDARD = LVDS_33;
NET "data_n[0]"  LOC = D17 | IOSTANDARD = LVDS_33;
NET "data_p[1]"  LOC = D15 | IOSTANDARD = LVDS_33;
NET "data_p[2]"  LOC = C17 | IOSTANDARD = LVDS_33;
NET "data_p[3]"  LOC = B16 | IOSTANDARD = LVDS_33;
NET "data_p[4]"  LOC = C15 | IOSTANDARD = LVDS_33;
NET "data_p[5]"  LOC = B14 | IOSTANDARD = LVDS_33;
NET "data_p[6]"  LOC = C13 | IOSTANDARD = LVDS_33;
NET "data_p[7]"  LOC = D14 | IOSTANDARD = LVDS_33;
NET "data_p[8]"  LOC = C5  | IOSTANDARD = LVDS_33;
NET "data_p[9]"  LOC = B6  | IOSTANDARD = LVDS_33;
NET "data_p[10]" LOC = C7  | IOSTANDARD = LVDS_33;
NET "data_p[11]" LOC = B8  | IOSTANDARD = LVDS_33;
NET "data_p[12]" LOC = C9  | IOSTANDARD = LVDS_33;
NET "data_p[13]" LOC = B10 | IOSTANDARD = LVDS_33;
NET "data_p[14]" LOC = D11 | IOSTANDARD = LVDS_33;
NET "data_p[15]" LOC = B18 | IOSTANDARD = LVDS_33;
NET "G_TX_OUT"            LOC = AB4 | IOSTANDARD = LVCMOS33;#LVCMOS18;  
####################### ETHERNET ################################################
NET "G_MD_CLK_OUT"  LOC = AA2 | IOSTANDARD = LVCMOS33;#LVCMOS18;
NET "G_MD_IO_OUT"   LOC = AB3 | IOSTANDARD = LVCMOS33;#LVCMOS18;
NET "G_RES_ETH_OUT" LOC = T15 | IOSTANDARD = LVCMOS33;#LVCMOS18;
####################### RX       ######################################
#NET "G_RX_CLK_IN"     LOC = Y11 | IOSTANDARD = LVCMOS18;
#NET "G_RX_DATA_IN[0]" LOC = Y3  | IOSTANDARD = LVCMOS18;
#NET "G_RX_DATA_IN[1]" LOC = W8  | IOSTANDARD = LVCMOS18;
#NET "G_RX_DATA_IN[2]" LOC = W4  | IOSTANDARD = LVCMOS18;
#NET "G_RX_DATA_IN[3]" LOC = U9  | IOSTANDARD = LVCMOS18;
#NET "G_RX_DATA_IN[4]" LOC = V7 | IOSTANDARD = LVCMOS18;
#NET "G_RX_DATA_IN[5]" LOC = V5 | IOSTANDARD = LVCMOS18;
#NET "G_RX_DATA_IN[6]" LOC = W9 | IOSTANDARD = LVCMOS18;
#NET "G_RX_DATA_IN[7]" LOC = U6 | IOSTANDARD = LVCMOS18;
#NET "G_RX_EN_IN" LOC = Y4 | IOSTANDARD = LVCMOS18;
#NET "G_RX_ER_IN" LOC = Y8 | IOSTANDARD = LVCMOS18;
######################   TX       ################################
NET G_TX_CLK_IN      LOC = W12  | IOSTANDARD = LVCMOS33;#LVCMOS18; #R11; -    
NET G_TX_EN_OUT      LOC = AB16 | IOSTANDARD = LVCMOS33;#LVCMOS18;
NET G_TX_ER_OUT      LOC = AB18 | IOSTANDARD = LVCMOS33;#LVCMOS18;
NET G_TX_DATA_OUT[0] LOC = AA18 | IOSTANDARD = LVCMOS33;#LVCMOS18;
NET G_TX_DATA_OUT[1] LOC = AB14 | IOSTANDARD = LVCMOS33;#LVCMOS18;
NET G_TX_DATA_OUT[2] LOC = AA16 | IOSTANDARD = LVCMOS33;#LVCMOS18;
NET G_TX_DATA_OUT[3] LOC = W14  | IOSTANDARD = LVCMOS33;#LVCMOS18;
#NET G_TX_DATA_OUT[4] LOC = T16  | IOSTANDARD = LVCMOS18;
#NET G_TX_DATA_OUT[5] LOC = Y14  | IOSTANDARD = LVCMOS18;
#NET G_TX_DATA_OUT[6] LOC = V15  | IOSTANDARD = LVCMOS18;
#NET G_TX_DATA_OUT[7] LOC = AA14 | IOSTANDARD = LVCMOS18;
####################### LEDS #####################################################
NET "G_TEST_TX_OUT[0]" LOC = D6  | SLEW = FAST | IOSTANDARD = LVCMOS33;#LVCMOS18;
NET "G_TEST_TX_OUT[1]" LOC = C6  | SLEW = FAST | IOSTANDARD = LVCMOS33;#LVCMOS18;
NET "G_TEST_TX_OUT[2]" LOC = D7  | SLEW = FAST | IOSTANDARD = LVCMOS33;#LVCMOS18;