ERROR:HDLCompiler:104 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 136: Cannot find <proc_common_pkg> in library <proc_common_v3_00_a>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 147: <clog2> is not declared.
ERROR:HDLCompiler:854 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 138: Unit <dynshreg_f> ignored due to previous errors.
ERROR:HDLCompiler:104 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 155: Cannot find <family_support> in library <proc_common_v3_00_a>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
ERROR:HDLCompiler:374 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 158: Entity <dynshreg_f> is not yet compiled.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 160: <families_type> is not declared.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 162: <boolean> is not declared.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 164: <boolean> is not declared.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 168: <positive> is not declared.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 169: <positive> is not declared.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 171: <n> is not declared.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 172: <n> is not declared.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 175: <boolean> is not declared.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 186: <boolean> is not declared.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 188: <natural> is not declared.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 190: <a> is not declared.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 200: <bit_vector> is not declared.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 204: <std_ulogic> is not declared.
ERROR:HDLCompiler:69 - "D:\users\andrey\projectsnew\src\dynshreg_f.vhd" Line 205: <std_ulogic> is not declared.
ISE 14.1 lite core

она в work у вас, сделайте так как написано тут http://forums.xilinx.com/t5/Embedded-Devel...ound/td-p/14738

'PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/I_OR_CS/USE_MUXCY_OR_GEN.BUS_WIDTH_FOR
_GEN[0].OR_BITS_I' with type 'or_muxcy' could not be resolved. A pin name
misspelling can cause this, a missing edif or ngc file, case mismatch between
the block name and the edif or ngc file name, or the misspelling of a type
name. Symbol 'or_muxcy' is not supported in target 'spartan3'.