int main( void )
{
volatile unsigned int i;

WDTCTL = WDTPW+WDTHOLD; // Stop WDT
FLL_CTL0 |= XCAP11PF; // Configure load caps

// Wait for xtal to stabilize
do
{
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0x47FF; i > 0; i--); // Time for flag to set
}
while ((IFG1 & OFIFG)); // OSCFault flag still set?



//SPI init
P1SEL |= BIT6+BIT7; // SPI1pins select
P2SEL |= BIT0; // SPI_CLK pin select
UCA1CTL1 = UCSWRST; // **Put state machine in reset**
UCA1CTL0 |= UCSYNC+UCCKPL+UCMSB; //3-pin, 8-bit SPI master
UCA1CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
IE2 |= UCA0RXIE; // Enable USCI_A0 RX interrupt

//while(!(P3IN&0x01)); // If clock sig from mstr stays low,
// it is not yet in SPI mode

//PIO init

P1DIR |= BIT5; // P1.5 output: BUSY signal
P1IE |= BIT4; // P1.4 Interrupt enabled CONVST signal
P1IES &= BIT4; // P2.7 hi/low edge
P1IFG &= ~BIT4; // P2.7 IFG Cleared

_BIS_SR(LPM4_bits + GIE); // Enter LPM4, enable interrupts

return 0;
}